公开(公告)号：US08208282B2

公开(公告)日：2012-06-26

申请号：US12899634

申请日：2010-10-07

Applicant: Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

Inventor： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

IPC: G11C11/36

CPC classification number: G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

Abstract: A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.

Abstract translation: 提供了一种存储单元，其包括第一导体，第二导​​体，能够提供基本上单向电流的转向元件，以及与该转向元件串联耦合的状态变化元件。 状态改变元件能够保持编程状态，并且转向元件和状态改变元件彼此垂直对准。 还提供其他方面。

公开(公告)号：US20110019467A1

公开(公告)日：2011-01-27

申请号：US12899634

申请日：2010-10-07

Applicant: Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

Inventor： Mark G. Johnson ,  Thomas H. Lee ,  Vivek Subramanian ,  Paul Michael Farmwald ,  James M. Cleeves

IPC: G11C11/00

CPC classification number: G11C17/06 ,  G11C11/5692 ,  G11C13/003 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2481 ,  H01L45/1233 ,  H01L45/16

Abstract: A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.

Abstract translation: 提供了一种存储单元，其包括第一导体，第二导​​体，能够提供基本上单向电流的转向元件，以及与该转向元件串联耦合的状态变化元件。 状态改变元件能够保持编程状态，并且转向元件和状态改变元件彼此垂直对准。 还提供其他方面。

公开(公告)号：US07603244B2

公开(公告)日：2009-10-13

申请号：US12171281

申请日：2008-07-10

Applicant: Stanley Wang ,  Bendik Kleveland ,  Thomas H. Lee

Inventor： Stanley Wang ,  Bendik Kleveland ,  Thomas H. Lee

IPC: G06F19/00

CPC classification number: H03L7/099

Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

Abstract translation: 一种用于校准VCO（10,40）的偏置电流以使相位噪声最小化的校准电路（20,50）和方法（60）。 校准电路（20,50）在偏置电流超过预定范围的同时监视VCO（10,40）的共模节点处的平均电压。 校准电路（20,50）识别与最小平均共模电压相关联的偏置电流，并利用该偏置电流来校准VCO（10,40）的偏置晶体管。

公开(公告)号：US20090197557A1

公开(公告)日：2009-08-06

申请号：US12012714

申请日：2008-02-04

Applicant: Thomas H. Lee ,  Bendik Kleveland

Inventor： Thomas H. Lee ,  Bendik Kleveland

IPC: H04B1/18

CPC classification number: H01Q25/00 ,  H01Q21/24 ,  H04B7/0825

Abstract: A differential diversity antenna is provided. In one embodiment, a differential diversity antenna is used in a wireless system comprising receiver circuitry. (and, in another embodiment, transmission circuitry). The differential diversity antenna comprises a plurality of antenna components that are aligned non-collinearly to achieve diversity. In another embodiment, the differential diversity antenna is used with a second differential diversity antenna. Other embodiments are disclosed, and each of the embodiments can be used alone or together in combination.

Abstract translation: 提供差分分集天线。 在一个实施例中，在包括接收机电路的无线系统中使用差分分集天线。 （并且在另一个实施例中为传输电路）。 差分分集天线包括非线性对准以实现分集的多个天线分量。 在另一个实施例中，差分分集天线与第二差分分集天线一起使用。 公开了其它实施例，并且每个实施例可以单独使用或组合使用。

公开(公告)号：US20080278243A1

公开(公告)日：2008-11-13

申请号：US11801199

申请日：2007-05-08

Applicant: Stanley Wang ,  Thomas H. Lee

Inventor： Stanley Wang ,  Thomas H. Lee

IPC: H03L7/18

CPC classification number: H03L7/199 ,  H03L7/0891 ,  H03L7/10

Abstract: A frequency synthesizer (50, 70) including an edge-detection circuit (51, 60) for disabling elements of the frequency synthesizer (50, 70) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer (50, 70) and enables elements of the frequency synthesizer (50, 70) upon the detection of the transition edge.

Abstract translation: 一种频率合成器（50,70），包括用于在启动之前禁用频率合成器（50,70）的元件的边缘检测电路（51,60）。 边缘检测电路检测频率合成器（50,70）的参考时钟信号（ref_clk）的过渡沿，并且在检测到过渡边缘时使能频率合成器（50,70）的元件。

公开(公告)号：US07199418B2

公开(公告)日：2007-04-03

申请号：US10254326

申请日：2002-09-25

Applicant: Thomas H. Lee

Inventor： Thomas H. Lee

IPC: H01L27/108

CPC classification number: G11C11/36 ,  H01L23/5252 ,  H01L27/10 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/8615 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract translation: 公开了具有第一和第二类型半导体结的异质结构半导体器件。 异构结构被并入柱状和轨道堆叠存储器电路中，从而改善其正向和反向电流比。

公开(公告)号：US07177366B1

公开(公告)日：2007-02-13

申请号：US09947624

申请日：2001-09-06

Applicant: Joel L. Dawson ,  Thomas H. Lee

Inventor： Joel L. Dawson ,  Thomas H. Lee

IPC: H04I27/00

CPC classification number: H04L27/368 ,  H03F1/3247 ,  H03F1/3294 ,  H03F3/24 ,  H03F2200/336

Abstract: In an automatic phase alignment circuit for a Cartesian feedback amplifier, the phase error is regularly monitored. In various implementations, this approach is used to provide true and continuous phase alignment. Based on a relationship between the up-converted and down-converted signals, another implementation of the invention provides phase-alignment for quadrature-phase components of a baseband signal by arithmetically combining the quadrature-phase components and the feedback components continuously and, in response, continuously phase-adjusting signals in the feed-forward signal path. Another aspect of the present invention is directed to an approach for calculating phase error for that is caused by DC-offset interference which, in turn, manifest at the outputs of many analog functional blocks.

Abstract translation: 在用于笛卡尔反馈放大器的自动相位对准电路中，定期监视相位误差。 在各种实施方案中，该方法用于提供真实和连续的相位对准。 基于上转换信号和下变频信号之间的关系，本发明的另一实现方式通过连续地对正交相位分量和反馈分量进行算术组合来提供基带信号的正交相位分量的相位对准，作为响应 ，在前馈信号路径中连续地相位调整信号。 本发明的另一方面涉及一种用于计算由DC偏移干扰引起的相位误差的方法，其反过来表现为许多模拟功能块的输出。

公开(公告)号：US06881994B2

公开(公告)日：2005-04-19

申请号：US09927648

申请日：2001-08-13

Applicant: Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Petti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Brad Herner

Inventor： Thomas H. Lee ,  Vivek Subramanian ,  James M. Cleeves ,  Andrew J. Walker ,  Christopher J. Petti ,  Igor G. Kouznetzov ,  Mark G. Johnson ,  Paul Michael Farmwald ,  Brad Herner

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/822 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/06 ,  H01L27/10 ,  H01L27/112 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/8242

CPC classification number: H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract translation: 提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

公开(公告)号：US06867992B2

公开(公告)日：2005-03-15

申请号：US10342122

申请日：2003-01-13

Applicant: J. James Tringali ,  P. Michael Farmwald ,  Thomas H. Lee ,  Mark G. Johnson ,  Derek J. Bosch

Inventor： J. James Tringali ,  P. Michael Farmwald ,  Thomas H. Lee ,  Mark G. Johnson ,  Derek J. Bosch

IPC: G06K19/077 ,  G11C5/00 ,  G11C5/02 ,  G11C5/06

CPC classification number: G11C5/025 ,  G11C5/063

Abstract: In one embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, and first and second circuitry fabricated on the substrate and under the memory array. The first and second circuitry allow the modular memory device to interface with first and second varieties of host devices, respectively. In another embodiment, a modular memory device is presented comprising a substrate, a memory array fabricated above the substrate, memory array support circuitry fabricated on the substrate, and logic circuitry fabricated on the substrate and under the memory array.

Abstract translation: 在一个实施例中，呈现模块化存储器件，其包括衬底，在衬底上方制造的存储器阵列，以及在衬底上和存储器阵列下方制造的第一和第二电路。 第一和第二电路允许模块化存储器件分别与第一和第二种类型的主机设备接口。 在另一个实施例中，提出了一种模块化存储器件，其包括衬底，在衬底上方制造的存储器阵列，在衬底上制造的存储器阵列支持电路，以及在衬底上以及在存储器阵列之下的逻辑电路。

公开(公告)号：US06539072B1

公开(公告)日：2003-03-25

申请号：US09524402

申请日：2000-03-13

Applicant: Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

Inventor： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

IPC: H04L700

CPC classification number: H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

Abstract: Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

Abstract translation: 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。