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37 条记录 (耗时 0.021 秒)

    Composition and method for reducing allergen
    1.
    发明授权
    Composition and method for reducing allergen 失效
    降低过敏原的组合物和方法

    公开(公告)号：US08338404B2

    公开(公告)日：2012-12-25

    申请号：US11853401

    申请日：2007-09-11

    申请人： Tetsuo Nakano ,  Hideo Kawabe ,  Keiichirou Inui ,  Kouichi Waki

    发明人： Tetsuo Nakano ,  Hideo Kawabe ,  Keiichirou Inui ,  Kouichi Waki

    IPC分类号： A01N43/00 ,  A61K31/33

    CPC分类号： A61K31/401

    摘要： This invention relates to an allergen-reducing composition comprising a hydroxyproline derivative, a polymer thereof, or a salt of such a derivative or polymer, which is capable of reducing the allergenicity of mites, pollens, or other allergens and is capable of imparting functions of reducing allergenicity to fibers or textiles such as a carpet, a tatami mat, a bed cloth, a curtain, clothing, a stuffed animal, a mask, a filter material, or a dust bag for an electric vacuum cleaner without discoloration; and a method for reducing allergens using such composition.

    摘要翻译： 本发明涉及包含羟脯氨酸衍生物，其聚合物或这种衍生物或聚合物的盐的变应原减少组合物，其能够降低螨虫，花粉或其它过敏原的变应原性，并且能够赋予 减轻对诸如地毯，榻榻米，床布，窗帘，衣物，填充动物，面罩，过滤材料或用于电动吸尘器而不变色的防尘袋的纤维或纺织品的变应原性; 以及使用这种组合物减少过敏原的方法。

    Data transfer system and method
    3.
    发明授权
    Data transfer system and method 失效
    数据传输系统及方法

    公开(公告)号：US5870594A

    公开(公告)日：1999-02-09

    申请号：US963857

    申请日：1997-11-04

    申请人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

    发明人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

    IPC分类号： G06F13/42 ,  G06F1/12 ,  H04J3/06 ,  H04L7/02 ,  G06F1/06

    CPC分类号： H04L7/02

    摘要： The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

    摘要翻译： 通过根据通过检测采样偏差确定的误差信号的反馈来控制接收机采样时钟和主时钟之间的相位差，相对于用于发起发送的主时钟，连续地调整接收机处的数字信号采样定时 在启动操作和正常操作期间，从期望的基准定时的时钟定时。 通过将采样时钟设置在启动时的所需参考时序来补偿各个器件中的传播延迟散射。 通过在正常工作期间根据接收到的数字信号检测采样时钟定时与参考定时的偏差，然后根据检测结果连续校正采样时钟定时来补偿在器件工作期间引起的传播延迟散射。

    Bipolar-MOS IC with internal voltage generator and LSI device with internal voltage generator
    4.
    发明授权
    Bipolar-MOS IC with internal voltage generator and LSI device with internal voltage generator 失效
    具有内部电压发生器和具有内部电压发生器的LSI器件的双极MOS IC

    公开(公告)号：US5153452A

    公开(公告)日：1992-10-06

    申请号：US401849

    申请日：1989-08-30

    申请人： Masahiro Iwamura ,  Shigeya Tanaka ,  Tatsumi Yamauchi ,  Ikuro Masuda ,  Tetsuo Nakano

    发明人： Masahiro Iwamura ,  Shigeya Tanaka ,  Tatsumi Yamauchi ,  Ikuro Masuda ,  Tetsuo Nakano

    IPC分类号： H01L27/04 ,  G05F1/46 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/56 ,  H01L21/822 ,  H01L27/06

    CPC分类号： G11C11/565 ,  G05F1/465 ,  G11C5/147 ,  G11C16/30

    摘要： There are provided a bipolar-MOS IC device smaller than half-micron scale, and a combination of such IC device and external circuits. The IC device has an internal voltage generating circuit for generating an internal power source by using an external power source, the voltage of the internal power source being lower than that of the external power source. The internal voltage generating circuit includes an NPN transistor formed in an N-type region or N-type island within a P-type semiconductor substrate of the IC device, and a PMOS transistor formed in the N-type island. The collector of the NPN transistor and the source of the PMOS transistor are used as external power source terminals. The drain of the PMOS transistor is connected to the base of the NPN transistor. The gate is used as a control signal terminal. The emitter of the NPN transistor is used as an internal power source output terminal. A current path from the external power source input terminal and the internal power source output terminal is accordingly formed within the N-type island isolated from the P-type substrate.

    摘要翻译： 提供了小于半微米级的双极MOS集成电路，以及这些IC器件和外部电路的组合。 IC器件具有内部电压产生电路，用于通过使用外部电源产生内部电源，内部电源的电压低于外部电源的电压。 内部电压产生电路包括形成在IC器件的P型半导体衬底内的N型区域或N型岛中的NPN晶体管和形成在N型岛中的PMOS晶体管。 NPN晶体管的集电极和PMOS晶体管的源极用作外部电源端子。 PMOS晶体管的漏极连接到NPN晶体管的基极。 门用作控制信号端子。 NPN晶体管的发射极用作内部电源输出端子。 因此，在与P型基板隔离的N型岛中形成从外部电源输入端子和内部电源输出端子的电流路径。

    COMPOSITION AND METHOD FOR REDUCING ALLERGEN
    5.
    发明申请
    COMPOSITION AND METHOD FOR REDUCING ALLERGEN 失效
    用于减少过敏原的组合物和方法

    公开(公告)号：US20090069403A1

    公开(公告)日：2009-03-12

    申请号：US11853401

    申请日：2007-09-11

    申请人： Tetsuo Nakano ,  Hideo Kawabe ,  Keiichirou Inui ,  Kouchi Waki

    发明人： Tetsuo Nakano ,  Hideo Kawabe ,  Keiichirou Inui ,  Kouchi Waki

    IPC分类号： A61K31/401 ,  A61P37/08

    CPC分类号： A61K31/401

    摘要： This invention relates to an allergen-reducing composition comprising a hydroxyproline derivative, a polymer thereof, or a salt of such a derivative or polymer, which is capable of reducing the allergenicity of mites, pollens, or other allergens and is capable of imparting functions of reducing allergenicity to fibers or textiles such as a carpet, a tatami mat, a bed cloth, a curtain, clothing, a stuffed animal, a mask, a filter material, or a dust bag for an electric vacuum cleaner without discoloration; and a method for reducing allergens using such composition.

    摘要翻译： 本发明涉及包含羟脯氨酸衍生物，其聚合物或这种衍生物或聚合物的盐的变应原减少组合物，其能够降低螨虫，花粉或其它过敏原的变应原性，并且能够赋予 减轻对诸如地毯，榻榻米，床布，窗帘，衣物，填充动物，面罩，过滤材料或用于电动吸尘器而不变色的防尘袋的纤维或纺织品的变应原性; 以及使用这种组合物减少过敏原的方法。

    Data transfer system and method including tuning of a sampling clock used for latching data
    8.
    发明授权
    Data transfer system and method including tuning of a sampling clock used for latching data 失效
    数据传输系统和方法包括调整用于锁存数据的采样时钟

    公开(公告)号：US5737589A

    公开(公告)日：1998-04-07

    申请号：US308346

    申请日：1994-09-19

    申请人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

    发明人： Toshio Doi ,  Takehisa Hayashi ,  Tetsuo Nakano

    IPC分类号： G06F13/42 ,  G06F1/12 ,  H04J3/06 ,  H04L7/02 ,  G06F1/06

    CPC分类号： H04L7/02

    摘要： The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

    摘要翻译： 通过根据通过检测采样偏差确定的误差信号的反馈来控制接收机采样时钟和主时钟之间的相位差，相对于用于发起发送的主时钟，连续地调整接收机处的数字信号采样定时 在启动操作和正常操作期间，从期望的基准定时的时钟定时。 通过将采样时钟设置在启动时的所需参考时序来补偿各个器件中的传播延迟散射。 通过在正常工作期间根据接收到的数字信号检测采样时钟定时与参考定时的偏差，然后根据检测结果连续校正采样时钟定时来补偿在器件工作期间引起的传播延迟散射。