公开(公告)号：US06826702B1

公开(公告)日：2004-11-30

申请号：US09671690

申请日：2000-09-28

Applicant: Toshiyuki Shibuya

Inventor： Toshiyuki Shibuya

IPC: G06F132

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  Y02D10/126 ,  Y02D10/152

Abstract: A power consumption reducing method for a radio set is disclosed. A CPU 12 controls various parts of the radio set. A clock signal is fed out to the CPU 1, and its frequency is controlled according to a read signal SRU instructing the reading of data from the CPU 1.

Abstract translation: 公开了一种用于无线电设备的功耗降低方法。 CPU 12控制无线电设备的各个部分。 时钟信号被送出到CPU 1，并且根据指示从CPU 1读取数据的读取信号SRU来控制其频率。

公开(公告)号：US06804792B2

公开(公告)日：2004-10-12

申请号：US09779554

申请日：2001-02-09

Applicant: Hirofumi Nishikawa

Inventor： Hirofumi Nishikawa

IPC: G06F132

CPC classification number: G06F1/3265 ,  G06F1/3203 ,  G09G2330/022 ,  Y02D10/153 ,  Y02D50/20

Abstract: A computer is connected to an external device and outputs a command to the external device to shift the external device to a power saving state. The computer comprises an operating system generating a first power saving command for shifting the external device to a first power saving state when a non-operation time reaches a first time, a driver converting the first power saving command into a second power saving command for shifting the external device to a second power saving state in which power consumption is lower than the first power saving state. The converted second power saving command is output to the external device.

Abstract translation: 计算机连接到外部设备，并向外部设备输出命令以将外部设备移动到省电状态。 计算机包括操作系统，当非操作时间到达第一时间时，产生第一省电命令，用于将外部设备转换到第一省电状态;驾驶员将第一省电命令转换为第二省电命令以进行换档 该外部设备处于功率低于第一省电状态的第二省电状态。 转换的第二省电命令被输出到外部设备。

公开(公告)号：US06785829B1

公开(公告)日：2004-08-31

申请号：US09608160

申请日：2000-06-30

Applicant: Varghese George ,  Robert L. Farrell

Inventor： Varghese George ,  Robert L. Farrell

IPC: G06F132

CPC classification number: G06F1/3296 ,  G06F1/08 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: A power control circuit an corresponding technique for adjusting operating frequency and/or supply voltage in sections of a single electronic device while maintaining substantially constant operating frequency and/or supply voltage in the other sections in the electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is connected to an external power source. As a result, the electronic device in the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage in some sections of the processor and not in the other sections during other situations.

Abstract translation: 一种功率控制电路，用于在单个电子设备的部分中调节工作频率和/或电源电压，同时在电子设备中的其它部分保持基本恒定的工作频率和/或电源电压的相应技术。 这种控制是基于通过确定硬件产品是否连接到外部电源的采用电子设备的硬件产品的操作环境。 结果，硬件产品中的电子设备能够在某些情况下以全频率和电压工作，并且在处理器的某些部分中以不降低的频率和/或电压工作，而在其他情况下不在其他部分。

公开(公告)号：US06757810B1

公开(公告)日：2004-06-29

申请号：US09657906

申请日：2000-09-08

Applicant: Masafumi Takahashi

Inventor： Masafumi Takahashi

IPC: G06F132

CPC classification number: G06F9/30079 ,  G06F1/3203 ,  G06F1/3237 ,  G06F9/3861 ,  Y02D10/128

Abstract: A control section sets a value “1” to a first flip-flop when a core executes a halt instruction. An OR circuit halts to output the clock. When the detection section detects an occurrence of the exception request, the control section copies the value “1” of the first flip-flop to a second flip-flop and then sets the value “0” to the first flip-flop to restart the supply of the clock to the core through the circuit. When detecting that the value “1” is set in the second flip-flop, the core judges that the state of the core was in the halt state when the exception request occurred, the core returns to the halt state after the completion of the exception handling by executing the halt instruction. When the second flip-flop does not store the value “1”, the core executes an instruction next to the address of the halt instruction.

Abstract translation: 当核心执行停止指令时，控制部分向第一触发器设置值“1”。 OR电路停止输出时钟。 当检测部分检测到异常请求的发生时，控制部分将第一触发器的值“1”复制到第二触发器，然后将值“0”设置到第一触发器以重新开始 通过电路将时钟提供给核心。 当检测到第二个触发器中设置了值“1”时，核心在发生异常请求时判断核心的状态处于停止状态，核心在完成异常之后返回到停止状态 通过执行停止指令进行处理。 当第二触发器不存储值“1”时，核心执行停止指令的地址旁边的指令。

公开(公告)号：US06754836B2

公开(公告)日：2004-06-22

申请号：US09730841

申请日：2000-12-07

Applicant: Yoshihiro Shimizu ,  Shinji Takeda ,  Sachiko Kawaguchi

Inventor： Yoshihiro Shimizu ,  Shinji Takeda ,  Sachiko Kawaguchi

IPC: G06F132

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171

Abstract: A microcomputer includes reloadable registers for prestoring count values corresponding to an ineffective interval and an effective interval which are set in accordance with the timing of a first edge and a second edge of a head pulse signal, and for setting these count values sequentially into a counter. Only when the first edge and second edge are input at predetermined timing through an event input terminal, that is, only when the head pulse signal is input, the interrupt signal is generated for changing the operation mode from a low current consumption mode to a normal operation mode. This makes it possible to prevent a mode transition due to noise, and reduce the power consumption of the microcomputer by making more effective use of the low current consumption mode by improving a mode transition identification rate.

Abstract translation: 微型计算机包括可重新加载的寄存器，用于对与无效间隔相对应的计数值和根据头部脉冲信号的第一个边沿和第二个边沿的定时设置的有效间隔进行预置，并将这些计数值顺序地设置到计数器中 。 仅当通过事件输入端子以预定的定时输入第一边缘和第二边缘时，即只有在输入了头部脉冲信号时才产生中断信号，以将操作模式从低电流消耗模式改变为正常 操作模式。 这使得可以防止由于噪声引起的模式转换，并且通过提高模式转换识别率，通过更有效地利用低电流消耗模式来降低微计算机的功耗。

公开(公告)号：US06715089B2

公开(公告)日：2004-03-30

申请号：US09767086

申请日：2001-01-22

Applicant: Andrej Zdravkovic

Inventor： Andrej Zdravkovic

IPC: G06F132

CPC classification number: G06F9/3869 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126

Abstract: A computer system has at least one processor and at least one queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of rates. A number of instructions in the queue is measured. The optimum clock rate is selected based on in part the determined number of queued instructions.

Abstract translation: 计算机系统具有至少一个处理器和至少一个用于存储由处理器执行的指令的队列。 处理器能够以多个速率进行计时。 测量队列中的许多指令。 部分地基于确定的排队指令数量来选择最佳时钟速率。

公开(公告)号：US06715088B1

公开(公告)日：2004-03-30

申请号：US09501718

申请日：2000-02-10

Applicant: Yoshifusa Togawa

Inventor： Yoshifusa Togawa

IPC: G06F132

CPC classification number: G06F1/3203 ,  H04L12/12 ,  Y02D50/20 ,  Y02D50/40

Abstract: A power consumption control method for collectively controlling the power consumption of electronic apparatuses connected to a network is provided. When an electronic apparatus is connected to the network, a management device performs power-saving control for the electronic apparatus. When the electronic apparatus is disconnected from the network, the electronic apparatus performs the power-saving control for itself. Thus, the power consumption of the clients connected to the network can be effectively reduced.

Abstract translation: 提供了用于共同控制连接到网络的电子设备的功耗的功耗控制方法。 当电子设备连接到网络时，管理设备对电子设备执行省电控制。 当电子设备与网络断开连接时，电子设备自身进行省电控制。 因此，可以有效地减少连接到网络的客户端的功耗。

公开(公告)号：US06687838B2

公开(公告)日：2004-02-03

申请号：US09733821

申请日：2000-12-07

Applicant: Doron Orenstien ,  Ronny Ronen

Inventor： Doron Orenstien ,  Ronny Ronen

IPC: G06F132

CPC classification number: G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/30083 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/3851 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.

Abstract translation: 系统和相应的方法使用“处理器慢速模式”在单个线程或多线程环境中使用PAUSE指令作为低功耗提示。 一个实施例实际上降低了处理器时钟的频率。 另外一个实施例通过在N个时钟周期内门控M个时钟周期来实际上降低处理器时钟的频率。 当所有线程发出PAUSE指令时，处理器进入慢速模式并保持一段时间。 此后，处理器返回正常模式。 或者，诸如中断或异常的事件可以使处理器从慢速模式返回正常模式。

公开(公告)号：US06681332B1

公开(公告)日：2004-01-20

申请号：US09523610

申请日：2000-03-13

Applicant: Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

Inventor： Michael Byrne ,  Nicola O'Byrne ,  Colin Price ,  Derek Hummerston

IPC: G06F132

CPC classification number: G06F1/3209 ,  H03M1/002

Abstract: A method for placing a device in a reduced power-consumption mode of operation. The method comprises the steps of initializing a device select signal into a first logic state, asserting the device select signal in a second logic state, and returning the device select signal to the first logic state within a first predetermined time window. A device is also described that includes means for detecting logic state transitions at a device select input and a clock input, and means for changing operating mode of the device in response to a predetermined number of logic state transitions at the clock input, occurring between logic state transitions at the device select input.

Abstract translation: 一种用于将设备放置在降低的功耗操作模式中的方法。 该方法包括以下步骤：将设备选择信号初始化为第一逻辑状态，以第二逻辑状态断言设备选择信号，并在第一预定时间窗口内将设备选择信号返回到第一逻辑状态。 还描述了一种装置，其包括用于检测设备选择输入和时钟输入处的逻辑状态转换的装置，以及用于响应于时钟输入处的预定数量的逻辑状态转换来改变设备的工作模式的装置，发生在逻辑 设备选择输入的状态转换。

公开(公告)号：US06665806B1

公开(公告)日：2003-12-16

申请号：US09487783

申请日：2000-01-20

Applicant: Yutaka Shimizu

Inventor： Yutaka Shimizu

IPC: G06F132

CPC classification number: G06F1/3275 ,  G06F1/263 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/14 ,  Y02D10/171

Abstract: A portable information processing apparatus includes a memory, an AC/DC converter, a built-in battery, a power source detection mechanism, and a switch. The memory includes a main memory block and a sub memory block. The AC/DC converter converts an AC voltage to a DC voltage supplied to the memory. The built-in battery supplies a battery DC voltage supplied to the memory. The power source detection mechanism detects whether the apparatus operates with the converted AC to DC voltage or the battery DC voltage. The power source detection mechanism generates a detection signal when detecting the battery DC voltage. If the switch receives no detection signal from the power source detection mechanism, the switch supplies the converted AC to DC voltage and the battery DC voltage to the main and sub memory blocks. Otherwise, he switch shuts off a supply of the battery DC voltage to the sub memory block of the memory when receiving the detection signal from the power source detection mechanism.

Abstract translation: 便携式信息处理装置包括存储器，AC / DC转换器，内置电池，电源检测机构和开关。 存储器包括主存储块和子存储块。 AC / DC转换器将AC电压转换为提供给存储器的DC电压。 内置电池为电池提供直流电压。 电源检测机构检测设备是否以转换的AC至DC电压或电池DC电压工作。 检测电池直流电压时，电源检测机构产生检测信号。 如果交换机没有从电源检测机构接收到检测信号，则开关将转换的交流电转换为直流电压，将电池的直流电压提供给主存储器和副存储器。 否则，当接收到来自电源检测机构的检测信号时，他切换到存储器的副存储块中的电池DC电压供应。