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公开(公告)号：US20090172363A1
公开(公告)日：2009-07-02
申请号：US11965667
申请日：2007-12-27
Applicant: Doron Orenstien , Zeev Sperber , Robert Valentine , Benny Eitan
Inventor： Doron Orenstien , Zeev Sperber , Robert Valentine , Benny Eitan
IPC: G06F9/312
CPC classification number: G06F9/30043 , G06F9/30036 , G06F9/30112 , G06F9/30181 , G06F9/3824 , G06F9/3885
Abstract: When legacy instructions, that can only operate on smaller registers, are mixed with new instructions in a processor with larger registers, special handling and architecture are used to prevent the legacy instructions from causing problems with the data in the upper portion of the registers, i.e., the portion that they cannot directly access. In some embodiments, the upper portion of the registers are saved to temporary storage while the legacy instructions are operating, and restored to the upper portion of the registers when the new instructions are operating. A special instruction may also be used to disable this save/restore operation if the new instruction are not going to use the upper part of the registers.
Abstract translation: 当只能在较小寄存器上运行的传统指令与具有较大寄存器的处理器中的新指令混合时，使用特殊处理和架构来防止遗留指令在寄存器上部的数据引起问题，即 ，他们不能直接访问的部分。 在一些实施例中，当旧指令正在操作时，寄存器的上部保存到临时存储器中，并且当新指令正在操作时将寄存器的上部部分恢复到寄存器的上部。 如果新指令不会使用寄存器的上半部分，也可以使用特殊指令禁用此保存/恢复操作。
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公开(公告)号：US07152167B2
公开(公告)日：2006-12-19
申请号：US10317776
申请日：2002-12-11
Applicant: Tsvika Kurts , Doron Orenstien , Marcelo Yuffe
Inventor： Tsvika Kurts , Doron Orenstien , Marcelo Yuffe
CPC classification number: G06F13/4072 , Y02D10/14 , Y02D10/151
Abstract: An approach for data bus power control. Data input sense amplifiers of a request agent are enabled prior to a data phase of a transaction according to a data bus power control signal. Once enabled, the data input sense amplifiers can capture data provided during the data phase of the read transaction. Accordingly, the data input sense amplifiers of the request agent are disabled according to the power control signal once the data phase of the read transaction is complete.
Abstract translation: 数据总线功率控制方法。 根据数据总线功率控制信号，请求代理的数据输入读出放大器在事务的数据阶段之前启用。 一旦使能，数据输入读出放大器可以捕获在读取事务的数据阶段期间提供的数据。 因此，一旦读取事务的数据阶段完成，请求代理的数据输入读出放大器根据功率控制信号被禁用。
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公开(公告)号：US07114038B2
公开(公告)日：2006-09-26
申请号：US10040608
申请日：2001-12-28
Applicant: Doron Orenstien , Marcelo Yuffe
Inventor： Doron Orenstien , Marcelo Yuffe
IPC: G06F13/00
CPC classification number: G06F1/3237 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0831 , G06F2212/1028 , Y02D10/126 , Y02D10/128 , Y02D10/13 , Y02D10/151 , Y02D50/20
Abstract: For one embodiment, a computer system includes both high power and low power buses coupling a processor to a controller. When the processor is in a high power mode, its cache is snooped by the controller via the high power bus. When the processor is in a low power mode, its cache is snooped by the controller via the low power bus.
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公开(公告)号：US07096145B2
公开(公告)日：2006-08-22
申请号：US10038162
申请日：2002-01-02
Applicant: Doron Orenstien , Ronny Ronen
Inventor： Doron Orenstien , Ronny Ronen
IPC: G06F15/00
CPC classification number: G06F11/3024 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F11/3062 , G06F11/3096 , Y02D10/126 , Y02D10/172
Abstract: A system is described that includes a microprocessor and a thermal control subsystem. The microprocessor includes execution resources to support processing of instructions and consumes power. The microprocessor also includes at least one throttling mechanism to reduce the amount of heat generated by the microprocessor. The thermal control subsystem is configured to estimate an amount of power used by the microprocessor and to control the throttling mechanism based on the estimated amount of current power usage to ensure that junction temperature will not exceed the maximum allowed temperature.
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公开(公告)号：US08694758B2
公开(公告)日：2014-04-08
申请号：US11965667
申请日：2007-12-27
Applicant: Doron Orenstien , Zeev Sperber , Robert Valentine , Benny Eitan
Inventor： Doron Orenstien , Zeev Sperber , Robert Valentine , Benny Eitan
IPC: G06F9/34
CPC classification number: G06F9/30043 , G06F9/30036 , G06F9/30112 , G06F9/30181 , G06F9/3824 , G06F9/3885
Abstract: When legacy instructions, that can only operate on smaller registers, are mixed with new instructions in a processor with larger registers, special handling and architecture are used to prevent the legacy instructions from causing problems with the data in the upper portion of the registers, i.e., the portion that they cannot directly access. In some embodiments, the upper portion of the registers are saved to temporary storage while the legacy instructions are operating, and restored to the upper portion of the registers when the new instructions are operating. A special instruction may also be used to disable this save/restore operation if the new instruction are not going to use the upper part of the registers.
Abstract translation: 当只能在较小寄存器上运行的传统指令与具有较大寄存器的处理器中的新指令混合时，使用特殊处理和架构来防止遗留指令在寄存器上部的数据引起问题，即 ，他们不能直接访问的部分。 在一些实施例中，当旧指令正在操作时，寄存器的上部保存到临时存储器中，并且当新指令正在操作时将寄存器的上部部分恢复到寄存器的上部。 如果新指令不会使用寄存器的上半部分，也可以使用特殊指令禁用此保存/恢复操作。
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Patent Agency Ranking
公开(公告)号：US07613908B2
公开(公告)日：2009-11-03
申请号：US11710028
申请日：2007-02-23
Applicant: Shlomo Raikin , Gad Sheaffer , Doron Orenstien
Inventor： Shlomo Raikin , Gad Sheaffer , Doron Orenstien
IPC: G06F9/312
CPC classification number: G06F9/3004 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F9/526
Abstract: Controlling a reorder buffer (ROB) to selectively perform functional hardware lock disabling (HLD) is described. One apparatus embodiment includes a unit to enable an ROB to selectively disable a lock upon Identifying a lock acquire operation (LAO) associated with a critical section (CS) entry point, a unit to selectively retire the LAO, a unit to cause the ROB to selectively disable the lock, and a unit to snoop a buffer. The apparatus may, based on the snooping, selectively abort a transaction associated with the CS.
Abstract translation: 描述了控制重排序缓冲器（ROB）以选择性地执行功能性硬件锁定禁止（HLD）。 一个设备实施例包括一个单元，以使得ROB能够在识别与关键部分（CS）入口点相关联的锁定获取操作（LAO）时选择性地禁用锁定，该选择单元选择性地退出LAO，该单元使得ROB 选择性地禁用该锁，以及一个单元来窥探缓冲区。 该设备可以基于窥探，选择性地中止与CS相关联的事务。
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公开(公告)号：US07130966B2
公开(公告)日：2006-10-31
申请号：US11217474
申请日：2005-09-02
Applicant: Baruch Solomon , Ronny Ronen , Doron Orenstien
Inventor： Baruch Solomon , Ronny Ronen , Doron Orenstien
CPC classification number: G06F9/3814 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3836 , G06F9/3869 , G06F12/0875 , Y02D10/14 , Y02D10/152
Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.
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公开(公告)号：US07043405B2
公开(公告)日：2006-05-09
申请号：US10964413
申请日：2004-10-12
Applicant: Doron Orenstien , Ronny Ronen
Inventor： Doron Orenstien , Ronny Ronen
IPC: G06F13/00
CPC classification number: G06F9/4856 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/16 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24 , Y02D10/32 , Y02D50/20
Abstract: Distribution of processing activity across processing hardware based on power consumption and/or thermal considerations. One embodiment includes a plurality of processing units and a monitor to obtain monitor (e.g., power consumption, or temperature or some combination thereof) values from the processing units. The monitor transfers a process from one processing unit to another in response to the monitor values from the processing units.
Abstract translation: 基于功耗和/或热考虑分布处理硬件的处理活动。 一个实施例包括多个处理单元和监视器以从处理单元获得监视器（例如，功率消耗，或其温度或其组合）值。 响应于来自处理单元的监视值，监视器将处理从一个处理单元传送到另一处理单元。
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公开(公告)号：US08909901B2
公开(公告)日：2014-12-09
申请号：US12005770
申请日：2007-12-28
Applicant: Cristina Anderson , Mark Buxton , Doron Orenstien , Bob Valentine
Inventor： Cristina Anderson , Mark Buxton , Doron Orenstien , Bob Valentine
CPC classification number: G06F9/30032 , G06F7/76 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30167 , G06F9/30181 , G06F12/0875 , G06F2212/452
Abstract: In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values so that selected portions of the first and second source operands or a predetermined value can be stored into elements of a destination. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括接收置换指令，第一和第二源操作数和控制值的逻辑，以及基于至少两个控制值之间的操作执行置换操作，使得第一 并且可以将第二源操作数或预定值存储到目的地的元素中。 可以组合多个置换指令以执行有效的表查找。 描述和要求保护其他实施例。
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公开(公告)号：US20090172366A1
公开(公告)日：2009-07-02
申请号：US12005770
申请日：2007-12-28
Applicant: Cristina Anderson , Mark Buxton , Doron Orenstien , Bob Valentine
Inventor： Cristina Anderson , Mark Buxton , Doron Orenstien , Bob Valentine
CPC classification number: G06F9/30032 , G06F7/76 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30167 , G06F9/30181 , G06F12/0875 , G06F2212/452
Abstract: In one embodiment, the present invention includes logic to receive a permute instruction, first and second source operands, and control values, and to perform a permute operation based on an operation between at least two of the control values. Multiple permute instructions may be combined to perform efficient table lookups. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括接收置换指令，第一和第二源操作数和控制值的逻辑，以及基于至少两个控制值之间的操作来执行置换操作。 可以组合多个置换指令以执行有效的表查找。 描述和要求保护其他实施例。
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