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公开(公告)号：US07096145B2
公开(公告)日：2006-08-22
申请号：US10038162
申请日：2002-01-02
Applicant: Doron Orenstien , Ronny Ronen
Inventor： Doron Orenstien , Ronny Ronen
IPC: G06F15/00
CPC classification number: G06F11/3024 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F11/3062 , G06F11/3096 , Y02D10/126 , Y02D10/172
Abstract: A system is described that includes a microprocessor and a thermal control subsystem. The microprocessor includes execution resources to support processing of instructions and consumes power. The microprocessor also includes at least one throttling mechanism to reduce the amount of heat generated by the microprocessor. The thermal control subsystem is configured to estimate an amount of power used by the microprocessor and to control the throttling mechanism based on the estimated amount of current power usage to ensure that junction temperature will not exceed the maximum allowed temperature.
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公开(公告)号：US07130966B2
公开(公告)日：2006-10-31
申请号：US11217474
申请日：2005-09-02
Applicant: Baruch Solomon , Ronny Ronen , Doron Orenstien
Inventor： Baruch Solomon , Ronny Ronen , Doron Orenstien
CPC classification number: G06F9/3814 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3836 , G06F9/3869 , G06F12/0875 , Y02D10/14 , Y02D10/152
Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.
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公开(公告)号：US07043405B2
公开(公告)日：2006-05-09
申请号：US10964413
申请日：2004-10-12
Applicant: Doron Orenstien , Ronny Ronen
Inventor： Doron Orenstien , Ronny Ronen
IPC: G06F13/00
CPC classification number: G06F9/4856 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/16 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24 , Y02D10/32 , Y02D50/20
Abstract: Distribution of processing activity across processing hardware based on power consumption and/or thermal considerations. One embodiment includes a plurality of processing units and a monitor to obtain monitor (e.g., power consumption, or temperature or some combination thereof) values from the processing units. The monitor transfers a process from one processing unit to another in response to the monitor values from the processing units.
Abstract translation: 基于功耗和/或热考虑分布处理硬件的处理活动。 一个实施例包括多个处理单元和监视器以从处理单元获得监视器（例如，功率消耗，或其温度或其组合）值。 响应于来自处理单元的监视值，监视器将处理从一个处理单元传送到另一处理单元。
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公开(公告)号：US07159133B2
公开(公告)日：2007-01-02
申请号：US10759455
申请日：2004-01-16
Applicant: Doron Orenstien , Ronny Ronen
Inventor： Doron Orenstien , Ronny Ronen
IPC: G06F1/32
CPC classification number: G06F1/3228 , G06F1/324 , G06F1/3296 , G06F9/30083 , G06F9/3009 , G06F9/30189 , G06F9/3836 , G06F9/3851 , Y02D10/126 , Y02D10/172
Abstract: A system and corresponding method use a PAUSE instruction as a low power hint in a single threaded or multithreaded environment using “processor slow mode.” One embodiment actually lowers the frequency of the processor clock. Another embodiment virtually lowers the frequency of the processor clock by gating M clock cycles out of every N clock cycles. When all threads have issued a PAUSE instruction, the processor enters slow mode and remains there for a while. After this while, the processor returns to normal mode. Alternatively, an event, such as an interrupt or an exception, can cause the processor to return to normal mode from slow mode.
Abstract translation: 系统和相应的方法使用“处理器慢速模式”在单个线程或多线程环境中使用PAUSE指令作为低功耗提示。 一个实施例实际上降低了处理器时钟的频率。 另外一个实施例通过在N个时钟周期内门控M个时钟周期来实际上降低处理器时钟的频率。 当所有线程发出PAUSE指令时，处理器进入慢速模式并保持一段时间。 此后，处理器返回正常模式。 或者，诸如中断或异常的事件可以使处理器从慢速模式返回正常模式。
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公开(公告)号：US20060053245A1
公开(公告)日：2006-03-09
申请号：US11217474
申请日：2005-09-02
Applicant: Baruch Solomon , Ronny Ronen , Doron Orenstien
Inventor： Baruch Solomon , Ronny Ronen , Doron Orenstien
IPC: G06F12/00
CPC classification number: G06F9/3814 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3836 , G06F9/3869 , G06F12/0875 , Y02D10/14 , Y02D10/152
Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.
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Patent Agency Ranking
公开(公告)号：US20050050373A1
公开(公告)日：2005-03-03
申请号：US10964413
申请日：2004-10-12
Applicant: Doron Orenstien , Ronny Ronen
Inventor： Doron Orenstien , Ronny Ronen
CPC classification number: G06F9/4856 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/16 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24 , Y02D10/32 , Y02D50/20
Abstract: Distribution of processing activity across processing hardware based on power consumption and/or thermal considerations. One embodiment includes a plurality of processing units and a monitor to obtain monitor (e.g., power consumption, or temperature or some combination thereof) values from the processing units. The monitor transfers a process from one processing unit to another in response to the monitor values from the processing units.
Abstract translation: 基于功耗和/或热考虑分布处理硬件的处理活动。 一个实施例包括多个处理单元和监视器以从处理单元获得监视器（例如，功率消耗，或其温度或其组合）值。 响应于来自处理单元的监视值，监视器将处理从一个处理单元传送到另一处理单元。
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7.发明授权公开(公告)号：US06950903B2
公开(公告)日：2005-09-27
申请号：US09892566
申请日：2001-06-28
Applicant: Baruch Solomon , Ronny Ronen , Doron Orenstien
Inventor： Baruch Solomon , Ronny Ronen , Doron Orenstien
CPC classification number: G06F9/3814 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3836 , G06F9/3869 , G06F12/0875 , Y02D10/14 , Y02D10/152
Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.
Abstract translation: 用于处理器的功率感知前端单元可以包括禁用前端单元中的其他电路的UOP高速缓存。 在一个实施例中，当块高速缓存和指令高速缓存中的指令查找正在进行时，前端单元可以禁用指令同步电路，指令解码电路和可选地的指令获取电路。 如果指令查找表示未命中，则其后的禁用电路可以被使能。
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8.发明授权公开(公告)号：US07653786B2
公开(公告)日：2010-01-26
申请号：US11589803
申请日：2006-10-31
Applicant: Baruch Solomon , Ronny Ronen , Doron Orenstien
Inventor： Baruch Solomon , Ronny Ronen , Doron Orenstien
IPC: G06F12/08
CPC classification number: G06F9/3814 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3836 , G06F9/3869 , G06F12/0875 , Y02D10/14 , Y02D10/152
Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.
Abstract translation: 用于处理器的功率感知前端单元可以包括禁用前端单元中的其他电路的UOP高速缓存。 在一个实施例中，当块高速缓存和指令高速缓存中的指令查找正在进行时，前端单元可以禁用指令同步电路，指令解码电路和可选地的指令获取电路。 如果指令查找表示未命中，则其后的禁用电路可以被使能。
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9.发明申请公开(公告)号：US20070050554A1
公开(公告)日：2007-03-01
申请号：US11589803
申请日：2006-10-31
Applicant: Baruch Solomon , Ronny Ronen , Doron Orenstien
Inventor： Baruch Solomon , Ronny Ronen , Doron Orenstien
CPC classification number: G06F9/3814 , G06F1/3203 , G06F1/3243 , G06F1/3275 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3808 , G06F9/3836 , G06F9/3869 , G06F12/0875 , Y02D10/14 , Y02D10/152
Abstract: A power aware front-end unit for a processor may include a UOP cache that disables other circuitry within the front-end unit. In an embodiment, a front-end unit may disable instruction synchronization circuitry, instruction decode circuitry and, optionally, instruction fetch circuitry while instruction look-ups are underway in both a block cache and an instruction cache. If the instruction look-up indicates a miss, the disabled circuitry thereafter may be enabled.
Abstract translation: 用于处理器的功率感知前端单元可以包括禁用前端单元中的其他电路的UOP高速缓存。 在一个实施例中，当块高速缓存和指令高速缓存中的指令查找正在进行时，前端单元可以禁用指令同步电路，指令解码电路和可选地的指令获取电路。 如果指令查找表示未命中，则其后的禁用电路可以被使能。
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10.发明授权公开(公告)号：US06804632B2
公开(公告)日：2004-10-12
申请号：US10020568
申请日：2001-12-06
Applicant: Doron Orenstien , Ronny Ronen
Inventor： Doron Orenstien , Ronny Ronen
IPC: G06F906
CPC classification number: G06F9/4856 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/152 , Y02D10/16 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24 , Y02D10/32 , Y02D50/20
Abstract: Distribution of processing activity across processing hardware based on power consumption and/or thermal considerations. One embodiment includes a plurality of processing units and a monitor to obtain monitor (e.g., power consumption, or temperature or some combination thereof) values from the processing units. The monitor transfers a process from one processing unit to another in response to the monitor values from the processing units.
Abstract translation: 基于功耗和/或热考虑分布处理硬件的处理活动。 一个实施例包括多个处理单元和监视器以从处理单元获得监视器（例如，功率消耗，或其温度或其组合）值。 响应于来自处理单元的监视值，监视器将处理从一个处理单元传送到另一处理单元。
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