公开(公告)号：US07879704B2

公开(公告)日：2011-02-01

申请号：US11674529

申请日：2007-02-13

申请人： Nobutoshi Arai ,  Hiroshi Iwata ,  Seizo Kakimoto

发明人： Nobutoshi Arai ,  Hiroshi Iwata ,  Seizo Kakimoto

IPC分类号： H01L21/425

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332

摘要： A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each particle is covered with a second material (e.g., silver oxide) and formed of a third material (e.g., silver). The second material functions as a barrier against passage of electric charges, and the third material has a function of retaining electric charges. The third material is introduced into the medium by, for example, a negative ion implantation method.

摘要翻译： 记忆功能体具有介于第一导体（例如，导电基板）和第二导体（例如电极）之间并由第一材料（例如氧化硅或氮化硅）组成的介质。 介质含有颗粒。 每个颗粒被第二材料（例如氧化银）覆盖并由第三种材料（例如银）形成。 第二材料用作阻止电荷通过的屏障，第三材料具有保持电荷的功能。 第三种材料通过例如负离子注入法引入介质中。

公开(公告)号：US07176526B2

公开(公告)日：2007-02-13

申请号：US10899183

申请日：2004-07-27

申请人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

发明人： Hiroshi Iwata ,  Akihide Shibata ,  Seizo Kakimoto ,  Kouichiro Adachi ,  Masayuki Nakano

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103, part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105, and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105. At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A–A′. An angle between the second surface and a surface of the isolation region is 80 degrees or less.

摘要翻译： 半导体器件1910包括包括隔离区域101和有源区域102的半导体衬底100，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106。 源极区域106和漏极区域106中的至少一个具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。

公开(公告)号：US07084465B2

公开(公告)日：2006-08-01

申请号：US10451744

申请日：2001-12-26

申请人： Akihide Shibata ,  Hiroshi Iwata ,  Seizo Kakimoto

发明人： Akihide Shibata ,  Hiroshi Iwata ,  Seizo Kakimoto

IPC分类号： H01L31/113

CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L21/823878 ,  H01L21/823892

摘要： There is provided a semiconductor device including DTMOS and a substrate variable-bias transistor and a portable electronic device both operable with reduced power consumption. N-type deep well regions are formed in one P-type semiconductor substrate. The N-type deep well regions are electrically isolated by the P-type semiconductor substrate. Over the N-type deep well regions, a P-type deep well region and a P-type shallow well region are formed to fabricate an N-type substrate variable-bias transistor. Over the N-type deep well region, an N-type shallow well region is formed to fabricate a P-type substrate variable-bias transistor. Further a P-type DTMOS and an N-type DTMOD are fabricated.

摘要翻译： 提供了包括DTMOS和基板可变偏置晶体管的半导体器件以及可以以降低的功耗进行操作的便携式电子设备。 在一个P型半导体衬底中形成N型深阱区。 N型深阱区域由P型半导体衬底电隔离。 在N型深井区域中，形成P型深井区域和P型浅井区域，以制造N型衬底可变偏压晶体管。 在N型深井区域上，形成N型浅井区，以制造P型衬底可变偏压晶体管。 此外，还制作了P型DTMOS和N型DTMOD。

公开(公告)号：US06969893B2

公开(公告)日：2005-11-29

申请号：US10416856

申请日：2001-11-13

申请人： Akihide Shibata ,  Hiroshi Iwata ,  Seizo Kakimoto

发明人： Akihide Shibata ,  Hiroshi Iwata ,  Seizo Kakimoto

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L21/76229 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/0921

摘要： There is provided a semiconductor device of low power consumption and high reliability having DTMOS' and substrate-bias variable transistors, and portable electronic equipment using the semiconductor device. On a semiconductor substrate (11), trilayer well regions (12, 14, 16; 13, 15, 16) are formed, and DTMOS' (29, 30) and substrate-bias variable transistors (27, 28) are provided in the shallow well regions (16, 17). Large-width device isolation regions (181, 182, 183) are provided at boundaries forming PNP, NPN or NPNP structures, where a small-width device isolation region (18) is provided on condition that well regions on both sides are of an identical conductive type. Thus, a plurality of well regions of individual conductive types where substrate-bias variable transistors (27, 28) of individual conductive types are provided can be made electrically independent of one another, allowing the power consumption to be reduced. Besides, the latch-up phenomenon can be suppressed.

摘要翻译： 提供了具有DTMOS和衬底偏置可变晶体管的低功耗和高可靠性的半导体器件，以及使用该半导体器件的便携式电子设备。 在半导体衬底（11）上，形成三层阱区域（12,14,16,13,15,16），并且在所述半导体衬底（11）中提供DTMOS'（29,30）和衬底偏置可变晶体管（27,28） 浅井区域（16,17）。 在形成PNP，NPN或NPNP结构的边界处提供大宽度器件隔离区（181,182,183），其中在两侧的阱区具有相同的条件下提供小宽度器件隔离区（18） 导电型。 因此，提供各种导电类型的衬底偏置可变晶体管（27,28）的各种导电类型的多个阱区域可以彼此电独立，从而允许降低功耗。 此外，可以抑制闩锁现象。

公开(公告)号：US06515340B2

公开(公告)日：2003-02-04

申请号：US09917954

申请日：2001-07-31

申请人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

发明人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L21/2257 ,  H01L27/088 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/78654

摘要： A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.

公开(公告)号：US06426532B1

公开(公告)日：2002-07-30

申请号：US09720714

申请日：2001-04-19

申请人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

发明人： Hiroshi Iwata ,  Seizo Kakimoto ,  Masayuki Nakano ,  Kouichiro Adachi

IPC分类号： H01L31119

CPC分类号： H01L29/783 ,  H01L21/84 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/78654

摘要： A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.

摘要翻译： 根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅电极的侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖对应的器件隔离区的一部分的第二导电类型半导体层，作为源区和/或漏区的第二导电类型半导体层。 栅电极和第一导电类型半导体层彼此电连接。 第二导电类型半导体层设置在第一导电类型半导体层之上，并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。

公开(公告)号：US5926741A

公开(公告)日：1999-07-20

申请号：US888470

申请日：1997-07-07

申请人： Toshimasa Matsuoka ,  Masayuki Nakano ,  Hiroshi Iwata ,  Seizo Kakimoto

发明人： Toshimasa Matsuoka ,  Masayuki Nakano ,  Hiroshi Iwata ,  Seizo Kakimoto

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L21/31

CPC分类号： H01L21/28202 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/02301 ,  H01L21/28211 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/518

摘要： In a method of forming gate dielectric films, a surface of a Si wafer is first cleaned in an inert gas ambient into a clean state having no naturally oxidized films. Then, after replacing the inert gas ambient with an oxidizing gas containing no nitrogen without exposing the wafer to air, the wafer is heated in the replaced ambient to form a first silicon oxide film on the silicon surface. Then, the ambient is again replaced with an oxidizing gas containing nitrogen, and the wafer is heated in the replaced ambient to form a first oxynitride film between the first silicon oxide film and the silicon. Thereafter, re-oxidation of the wafer is performed in an ambient of oxidizing gas containing no nitrogen to form a second silicon oxide film between the first oxynitride film and the silicon.

摘要翻译： 在形成栅极电介质膜的方法中，首先将Si晶片的表面在惰性气体环境中清洁成没有天然氧化膜的清洁状态。 然后，在用不含氮的氧化气体代替惰性气体环境而不将晶片暴露于空气之后，在更换的环境中加热晶片，以在硅表面上形成第一氧化硅膜。 然后，再次用含有氮的氧化气体代替环境，并且在更换的环境中加热晶片，以在第一氧化硅膜和硅之间形成第一氮氧化物膜。 此后，在不含氮的氧化气体的环境中进行晶片的再氧化，以在第一氮氧化物膜和硅之间形成第二氧化硅膜。

公开(公告)号：US5903029A

公开(公告)日：1999-05-11

申请号：US902673

申请日：1997-07-30

申请人： Shigeki Hayashida ,  Seizo Kakimoto

发明人： Shigeki Hayashida ,  Seizo Kakimoto

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/08 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/6659 ,  H01L29/0847 ,  H01L29/7833 ,  H01L21/2652

摘要： An insulated-gate field-effect transistor formed in a substrate of a first conductive type or in a well of the first conductive type formed in the substrate is provided. The transistor includes a channel region containing an impurity of the first conductive type; and a source-drain region containing an impurity of a second conductive type. The source-drain region further contains an impurity of the first conductive type; and a concentration of the impurity of the first conductive type contained in the source-drain region is greater than a concentration of the impurity of the first conductive type contained in the channel region but is less than a concentration of the impurity of the second conductive type contained in the source-drain region.

摘要翻译： 提供了形成在第一导电类型的衬底中或形成在衬底中的第一导电类型的阱中的绝缘栅场效应晶体管。 晶体管包括含有第一导电类型杂质的沟道区; 以及包含第二导电类型的杂质的源极 - 漏极区域。 源极 - 漏极区还包含第一导电类型的杂质; 并且源极 - 漏极区域中包含的第一导电类型的杂质的浓度大于沟道区域中包含的第一导电类型的杂质的浓度，但是小于第二导电类型的杂质的浓度 包含在源极 - 漏极区域中。

公开(公告)号：US07187043B2

公开(公告)日：2007-03-06

申请号：US10796963

申请日：2004-03-11

申请人： Nobutoshi Arai ,  Hiroshi Iwata ,  Seizo Kakimoto

发明人： Nobutoshi Arai ,  Hiroshi Iwata ,  Seizo Kakimoto

IPC分类号： H01L21/8238

CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L29/42332

摘要： A memory function body has a medium interposed between a first conductor (e.g., a conductive substrate) and a second conductor (e.g., an electrode) and consisting of a first material (e.g., silicon oxide or silicon nitride). The medium contains particles. Each particle is covered with a second material (e.g., silver oxide) and formed of a third material (e.g., silver). The second material functions as a barrier against passage of electric charges, and the third material has a function of retaining electric charges. The third material is introduced into the medium by, for example, a negative ion implantation method.

摘要翻译： 记忆功能体具有介于第一导体（例如，导电基板）和第二导体（例如电极）之间并由第一材料（例如氧化硅或氮化硅）组成的介质。 介质含有颗粒。 每个颗粒被第二材料（例如氧化银）覆盖并由第三种材料（例如银）形成。 第二材料用作阻止电荷通过的屏障，第三材料具有保持电荷的功能。 第三种材料通过例如负离子注入法引入介质中。

公开(公告)号：US20060154432A1

公开(公告)日：2006-07-13

申请号：US10528052

申请日：2003-09-18

申请人： Nobutoshi Arai ,  Hiroshi Iwata ,  Seizo Kakimoto

发明人： Nobutoshi Arai ,  Hiroshi Iwata ,  Seizo Kakimoto

IPC分类号： H01L29/768

CPC分类号： H01L29/8615 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/10 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/1608 ,  Y10S438/90

摘要： A resistance-changing function body includes an object made of a first substance and interposed between a first electrode and a second electrode, and a plurality of particles made of a second substance and arranged within the object so that an electrical resistance between the first electrode and the second electrode is changed before and after application of a specified voltage to between the first electrode and the second electrode. The first substance makes an electrical barrier against the second substance. With this constitution, by applying a specified voltage to between the first electrode and the second electrode, the electrical resistance can be changed depending on a state of the particles made of the second substance. Also, by virtue of a simple structure, a resistance-changing function body of small size is provided with low cost.

摘要翻译： 电阻变化功能体包括由第一物质制成的物体，介于第一电极和第二电极之间，以及多个由第二物质制成的颗粒并且布置在物体内，使得第一电极和第二电极之间的电阻 在第一电极和第二电极之间施加指定电压之前和之后改变第二电极。 第一物质对第二物质产生电阻。 利用这种结构，通过在第一电极和第二电极之间施加规定的电压，可以根据由第二物质制成的粒子的状态来改变电阻。 另外，由于结构简单，所以以低成本提供小尺寸的电阻变化功能体。