公开(公告)号：US08547502B2

公开(公告)日：2013-10-01

申请号：US12254852

申请日：2008-10-21

Applicant: Norio Nakazato ,  Kimihiko Sudo ,  Hiroshi Akai ,  Naoki Yotsumoto ,  Hiroshi Oyama ,  Shigeyuki Sasaki ,  Atsushi Hatakeyama ,  Takaaki Maruyama ,  Kouichi Tanabe

Inventor： Norio Nakazato ,  Kimihiko Sudo ,  Hiroshi Akai ,  Naoki Yotsumoto ,  Hiroshi Oyama ,  Shigeyuki Sasaki ,  Atsushi Hatakeyama ,  Takaaki Maruyama ,  Kouichi Tanabe

IPC: G02F1/13339

CPC classification number: H01L33/483 ,  H01L33/54 ,  H01L33/60 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00

Abstract: It is to provide a light source module capable of downsizing an edge-light type backlight in thickness and reducing the usage amount of resin. A method of manufacturing a light source module includes a process of preparing a substrate with a first reflector including a reflecting surface mounted thereon, a process of mounting a plurality of light emitting elements on the substrate, a process of mounting a wiring board having an electrode on the substrate, a process of connecting the electrode of the light emitting element and the electrode of the wiring board with metal wire, a process of mounting a second reflector having a reflecting surface on the wiring board, and a process of filling the space between the first reflector and the second reflector, with resin.

Abstract translation: 提供能够使边缘光型背光的厚度小型化并且减少树脂的使用量的光源模块。 一种制造光源模块的方法包括：制备具有安装在其上的反射表面的第一反射器的基板的处理，将多个发光元件安装在基板上的工艺，安装具有电极的布线板的工艺 在基板上，使用金属线将发光元件的电极和布线板的电极连接的过程，在布线基板上安装具有反射面的第二反射体的处理以及填充 第一反射器和第二反射器，具有树脂。

公开(公告)号：US20050263869A1

公开(公告)日：2005-12-01

申请号：US11138936

申请日：2005-05-25

Applicant: Naotaka Tanaka ,  Norio Nakazato ,  Takahiro Naito

Inventor： Naotaka Tanaka ,  Norio Nakazato ,  Takahiro Naito

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/48 ,  H01L23/485 ,  H01L23/495 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: To provide a very-low-cost and short-TAT connection structure superior in connection reliability in accordance with a method for three-dimensionally connecting a plurality of semiconductor chips at a shortest wiring length by using a through-hole electrode in order to realize a compact, high-density, and high-function semiconductor system. The back of a semiconductor chip is decreased in thickness up to a predetermined thickness through back-grinding, a hole reaching a surface-layer electrode is formed at a back position corresponding to a device-side external electrode portion through dry etching, a metallic deposit is applied to the sidewall of the hole and the circumference of the back of the hole, a metallic bump (protruded electrode) of another semiconductor chip laminated on the upper side is deformation-injected into the through-hole by compression bonding, and the metallic bump is geometrically caulked and electrically connected to the inside of a through-hole formed in an LSI chip. It is possible to realize a unique connection structure having a high reliability in accordance with the caulking action using the plastic flow of a metallic bump in a very-low-cost short-TAT process and provide a three-dimensional inter-chip connection structure having a high practicability.

Abstract translation: 为了提供一种根据用于通过使用通孔电极以最短布线长度三维连接多个半导体芯片的方法来提供优异的连接可靠性的极低成本和短TAT连接结构，以便实现 紧凑，高密度和高功能的半导体系统。 通过背面研磨，半导体芯片的背面的厚度减小到规定的厚度，通过干法蚀刻，在与设备侧的外部电极部对应的后方位置形成到达表层电极的孔，金属沉积物 施加到孔的侧壁和孔的背面的周围，层叠在上侧的另一半导体芯片的金属凸块（突出电极）通过压接而变形注入到通孔中，并且金属 凸块几何地被铆接并电连接到形成在LSI芯片中的通孔的内部。 可以在非常低成本的短TAT工艺中实现使用金属凸块的塑性流动的铆接动作具有高可靠性的独特的连接结构，并且提供一种三维芯片间连接结构，其具有 实用性高。

公开(公告)号：US06924549B2

公开(公告)日：2005-08-02

申请号：US10621411

申请日：2003-07-18

Applicant: Fujiaki Nose ,  Hiroshi Kikuchi ,  Satoshi Ueno ,  Norio Nakazato

Inventor： Fujiaki Nose ,  Hiroshi Kikuchi ,  Satoshi Ueno ,  Norio Nakazato

IPC: H01L23/50 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L23/64 ,  H01L23/66

CPC classification number: H01L23/642 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/5222 ,  H01L23/66 ,  H01L24/06 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/75 ,  H01L2223/6627 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78701 ,  H01L2224/78755 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/10162 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19033 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  Y10T29/49121 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.

Abstract translation: 公开了一种用于形成封装的装置，其中使用引线接合方法在其上安装了形成有高速LSI的半导体芯片。 封装包括半导体芯片，小于半导体芯片的主表面的管芯焊盘，密封构件，多个引线，每个引线包括外部端子部分和内部引线部分，以及多个接合线，用于连接形成在 半导体芯片和引线的内引线部分，每个内引线部分沿着远离密封部件的安装表面的方向弯曲，从而接近芯片侧焊盘的高度和接合位置的接合位置 内部引线部分彼此之间，从而可以缩短导线长度，并且可以抑制线部分的电感增加，并在高频信号输入/输出传输路径的各个部分获得阻抗匹配。

公开(公告)号：US06911734B2

公开(公告)日：2005-06-28

申请号：US10391746

申请日：2003-03-20

Applicant: Hiroshi Kikuchi ,  Norio Nakazato ,  Hideko Ando ,  Takashi Suga ,  Satoru Isomura ,  Takashi Kubo ,  Hiroyasu Sasaki ,  Masanori Fukuhara ,  Naotaka Tanaka ,  Fujiaki Nose

Inventor： Hiroshi Kikuchi ,  Norio Nakazato ,  Hideko Ando ,  Takashi Suga ,  Satoru Isomura ,  Takashi Kubo ,  Hiroyasu Sasaki ,  Masanori Fukuhara ,  Naotaka Tanaka ,  Fujiaki Nose

IPC: H01L23/66 ,  H05K1/02 ,  H05K3/36 ,  H01L23/34

CPC classification number: H05K1/0243 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32188 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/1903 ,  H01L2924/19106 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K3/361 ,  H05K2201/10522 ,  H05K2201/1053 ,  H05K2201/10659 ,  H05K2201/10681 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.

公开(公告)号：US5793611A

公开(公告)日：1998-08-11

申请号：US752009

申请日：1996-11-19

Applicant: Norio Nakazato ,  Shigeki Hirasawa ,  Shoji Masukawa ,  Heikichi Kuwahara

Inventor： Norio Nakazato ,  Shigeki Hirasawa ,  Shoji Masukawa ,  Heikichi Kuwahara

IPC: H05K7/20 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0201 ,  H05K1/0207 ,  H05K7/20509 ,  H05K1/0272 ,  H05K1/181 ,  H05K2201/0187 ,  H05K2201/0397 ,  H05K2201/062 ,  H05K2201/09063 ,  H05K2201/1028 ,  H05K2201/10416 ,  H05K2203/304

Abstract: An electronic device comprises a substrate having electronic parts, electric conductive wires for electrically connecting between the electronic parts, a front surface on which the electronic parts and electric conductive wires are mounted, a reverse surface and at least one electronic part back portion opposite to the electronic parts; and at least one high thermal conductivity member, a thermal conductivity coefficient thereof being higher than that of the substrate, the high thermal conductivity member being connected to the electronic part back portion while the high thermal conductivity member is opposite to the electronic parts in a substrate width direction to decrease a difference in temperature between the electronic parts.

Abstract translation: 电子设备包括具有电子部件的基板，用于电连接电子部件的导电线，安装有电子部件和导电线的前表面，反面以及与该电子部件相对的至少一个电子部件后部 电子零件; 和至少一个高导热性部件，其导热系数高于基板的导热系数，高导热性部件连接到电子部件背部，同时高导热性部件与基板中的电子部件相对 宽度方向以减小电子部件之间的温度差。

公开(公告)号：US5616520A

公开(公告)日：1997-04-01

申请号：US367490

申请日：1994-12-30

Applicant: Masahiko Nishiuma ,  Norio Nakazato ,  Hiroyuki Takahashi ,  Chiyoshi Kamada ,  Motoo Suwa

Inventor： Masahiko Nishiuma ,  Norio Nakazato ,  Hiroyuki Takahashi ,  Chiyoshi Kamada ,  Motoo Suwa

IPC: H01L21/60 ,  H01L23/10 ,  H01L23/367 ,  H01L23/433 ,  H01L23/485 ,  H01L23/66

CPC classification number: H01L24/16 ,  H01L23/10 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/433 ,  H01L23/66 ,  H01L24/11 ,  H01L24/13 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/45144 ,  H01L2224/73253 ,  H01L2224/749 ,  H01L2224/75 ,  H01L2224/75753 ,  H01L2224/78301 ,  H01L2224/81193 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011 ,  Y10T29/49144

Abstract: A semiconductor device is fabricated by forming first metal balls on electrode pads of a semiconductor chip. The first metal balls each can have a sharp tipped anchor. All of the anchors simultaneously flattened slightly only to the extent of equalizing the height thereof. The first metal balls are bonded to electrodes formed on a substrate with wirings by embedding the anchors into the electrodes. Alternatively, second metal balls can be formed on the electrodes which are then flattened to equalize the height thereof. The first metal balls, either with or without the anchors, are bonded to the second metal balls. The first and second metal balls are preferably heated during the bonding step to soften the second metal balls.

Abstract translation: 通过在半导体芯片的电极焊盘上形成第一金属球来制造半导体器件。 第一个金属球各自可以具有尖锐的尖头锚。 所有的锚点同样平坦化，只能达到使其高度均匀的程度。 通过将锚固件嵌入电极中，第一金属球通过布线与形成在基板上的电极结合。 或者，可以在电极上形成第二金属球，然后将其平坦化以使其高度均匀。 具有或不具有锚固件的第一金属球结合到第二金属球。 第一和第二金属球优选在接合步骤期间被加热以软化第二金属球。

公开(公告)号：US4459143A

公开(公告)日：1984-07-10

申请号：US451960

申请日：1982-12-21

Applicant: Makoto Nawata ,  Norio Nakazato ,  Sachihiro Yoshimatsu ,  Youichi Itou ,  Kengo Sugiyama ,  Yasuo Tasaka

Inventor： Makoto Nawata ,  Norio Nakazato ,  Sachihiro Yoshimatsu ,  Youichi Itou ,  Kengo Sugiyama ,  Yasuo Tasaka

IPC: F28F27/02 ,  F25J3/04 ,  F25J5/00 ,  F28F27/00

CPC classification number: F25J5/00 ,  F28F27/00 ,  F25J2210/40 ,  F25J2280/02

Abstract: A temperature control method for a reversing type heat exchanger group wherein an outlet temperature of reheating gas of an arbitrarily selected reversing type heat exchanger which serves as a reference in the reversing heat exchanger group is rendered equal in value to a reference control temperature set beforehand in such a manner so as to satisfy the sweeping temperature difference. The outlet temperatures of the reheating gas in the other reversing type heat exchangers of the reversing type heat exchanger group are rendered equal in value to the outlet temperature of the reheating gas in the reversing type heat exchanger serving as the reference. Thus, the temperature of the cold end of all of the reversing type heat exchangers of the reversing type heat exchanger group are caused to be balanced equally whereby ice and dry ice deposited on the feed water channels can be effectively removed by a sweeping action.

Abstract translation: 用于反转型热交换器组的温度控制方法，其中在换向换热器组中作为基准的任意选择的换向换热器的再加热气体的出口温度与预先设定的参考控制温度相等 以满足扫描温度差的方式。 反转型热交换器组的其他换向型热交换器中的再加热气体的出口温度与作为基准的换向型热交换器中的再加热气体的出口温度相等。 因此，使逆变型热交换器组的所有反向型热交换器的冷端的温度平衡地平衡，从而可以通过扫掠动作有效地去除沉积在给水通道上的冰和干冰。

公开(公告)号：US20100052149A1

公开(公告)日：2010-03-04

申请号：US12545465

申请日：2009-08-21

Applicant: Fujiaki Nose ,  Hiroshi Kikuchi ,  Norio Nakazato

Inventor： Fujiaki Nose ,  Hiroshi Kikuchi ,  Norio Nakazato

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49503 ,  H01L23/49513 ,  H01L23/49582 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/27013 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01026 ,  H01L2924/3512

Abstract: A semiconductor device includes: a die pad having a top surface; a plurality of leads arranged around the die pad; a semiconductor chip having a main surface, a back surface, and a plurality of pads formed to the main surface, and having the back surface fixedly adhered in opposing contact with the top surface of the die pad; a plurality of wires electrically connecting the plurality of pads of the semiconductor chip and the plurality of leads, respectively; and a sealing body sealing the semiconductor chip and the plurality of wires. In addition, a plurality of groove portions are formed to a chip-mounting region opposing the back surface of the semiconductor chip in the top surface of the die pad, and an adhesive for fixedly adhering the semiconductor chip to the top surface of the die pad is buried in the plurality of groove portions.

Abstract translation: 半导体器件包括：具有顶表面的管芯焊盘; 围绕芯片焊盘布置的多个引线; 半导体芯片，具有主表面，背面和形成在主表面上的多个焊盘，并且其背面固定地与芯片焊盘的顶表面相接触地粘附; 分别电连接半导体芯片的多个焊盘和多个引线的多个引线; 以及密封半导体芯片和多根导线的密封体。 此外，在与芯片安装区域相对的芯片安装区域形成多个槽部，该芯片安装区域与芯片的上表面的半导体芯片的背面相对，并且将用于将半导体芯片固定地粘附到芯片焊盘的顶面的粘合剂 被埋在多个槽部中。

公开(公告)号：US07671534B2

公开(公告)日：2010-03-02

申请号：US11527718

申请日：2006-09-27

Applicant: Yasushi Kinoshita ,  Norio Nakazato ,  Naoki Yotsumoto ,  Keisuke Nishimura ,  Daisuke Nakahara

Inventor： Yasushi Kinoshita ,  Norio Nakazato ,  Naoki Yotsumoto ,  Keisuke Nishimura ,  Daisuke Nakahara

IPC: H01J63/04 ,  H01J1/62 ,  F21V7/04

CPC classification number: G02B6/0021 ,  G02B6/0028

Abstract: When a long illuminant module is constructed, debonding of a bonded interface or bending occurs due to a difference in a magnitude of thermal deformation between a lens material and a metal substrate. In an illuminant module including light emitting elements, a substrate on which the light emitting elements are mounted, a transparent encapsulating resin which encapsulates the light emitting elements, and a lens material having cavities formed therein, in which the respective light emitting elements and transparent encapsulating resin are stored, notches are formed in a surface of the lens material on the side of the substrate, and the notch surfaces of the notches and the surface of the substrate are bonded using a bonding material.

Abstract translation: 当构造长的光源模块时，由于透镜材料和金属基板之间的热变形的大小的差异，发生接合界面的剥离或弯曲。 在包括发光元件的发光体模块中，安装有发光元件的基板，封装发光元件的透明封装树脂以及其中形成有空腔的透镜材料，其中各个发光元件和透明封装 存储树脂，在基板一侧的透镜材料的表面上形成切口，并且使用接合材料将切口的切口面和基板的表面接合。

公开(公告)号：US20090114958A1

公开(公告)日：2009-05-07

申请号：US12264936

申请日：2008-11-05

Applicant: Norio Nakazato ,  Nobuo Fujieda ,  Masayoshi Ishibashi ,  Midori Kato ,  Tadashi Arai ,  Takeo Shiba

Inventor： Norio Nakazato ,  Nobuo Fujieda ,  Masayoshi Ishibashi ,  Midori Kato ,  Tadashi Arai ,  Takeo Shiba

IPC: H01L29/78 ,  H01L21/311

CPC classification number: H01L21/4867 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K3/107 ,  H05K3/1258 ,  H05K2201/09036 ,  H05K2201/09254 ,  H01L2924/00

Abstract: A wiring board with an electronic device comprising a plurality of trenches arranged in parallel on a substrate, a common trench communicating the plurality of trenches with each other at one of their ends on the substrate, a metal layer formed at the bottom of the plurality of trenches, and an electrode layer connected with the metal layer and formed on a bottom of the common trench, wherein the electrode layer on the bottom of the common trench constitutes a source electrode or a drain electrode of a field effect transistor, whereby the wiring board and an electronic circuit having a good fine wire pattern and a good narrow gap between the patterns using a coating material can be formed, and a reduction for a cost of an organic thin film electronic device and the electronic circuit can be attained since they can be realized through a development of a printing technique.

Abstract translation: 一种具有电子装置的布线板，包括平行布置在基板上的多个沟槽，在所述基板的一端的一端将所述多个沟槽彼此连通的公共沟槽，形成在所述多个栅极的底部的金属层 沟槽，和与金属层连接并形成在公共沟槽的底部上的电极层，其中公共沟槽的底部上的电极层构成场效应晶体管的源电极或漏电极，由此布线板 并且可以形成具有良好细线图案和使用涂料的图案之间良好窄间隙的电子电路，并且可以实现有机薄膜电子器件和电子电路的成本降低，因为它们可以是 通过开发印刷技术实现。