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    GUIDE WIRE FOR ENDOSCOPE
    2.
    发明申请
    GUIDE WIRE FOR ENDOSCOPE 审中-公开
    内镜指南

    公开(公告)号：US20120078051A1

    公开(公告)日：2012-03-29

    申请号：US13242706

    申请日：2011-09-23

    申请人： Kenta SUZUKI ,  Junichi Kobayashi ,  Yasushi Kinoshita

    发明人： Kenta SUZUKI ,  Junichi Kobayashi ,  Yasushi Kinoshita

    IPC分类号： A61B1/00

    CPC分类号： A61M25/09 ,  A61B1/00098 ,  A61M2025/0008 ,  A61M2025/09075 ,  A61M2025/09083 ,  A61M2025/0915 ,  A61M2025/09166

    摘要： A guide wire includes a wire having an elongated body section and a distal portion decreasing in outer diameter from the body section. The guide wire may have a resin coating portion coating the body section and the distal portion and having a smooth outer surface; and a visually discernible mark provided at the resin coating portion. The body section may have a flexible portion which constitutes a part of the body section and lower in flexural rigidity than other portions of the body section different from the part, and the visually discernible mark is provided at a position of the resin coating portion at which the flexible portion is coated with the resin coating portion

    摘要翻译： 引导线包括具有细长主体部分和从主体部分减小到外径的远端部分的线。 引导线可以具有涂覆主体部分和远端部分并且具有光滑的外表面的树脂涂覆部分; 以及设置在树脂涂布部分处的视觉辨别标记。 身体部分可以具有柔性部分，其构成身体部分的一部分并且弯曲刚度低于与部分不同的身体部分的其他部分，并且视觉上可辨别的标记设置在树脂涂覆部分的位置处， 柔性部分涂覆有树脂涂层部分

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US07355265B2

    公开(公告)日：2008-04-08

    申请号：US10669655

    申请日：2003-09-25

    申请人： Yasushi Kinoshita

    发明人： Yasushi Kinoshita

    IPC分类号： H01L29/00

    CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L23/5286 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit comprising a power supply wiring and a ground wiring and a decoupling capacitor formed between the power supply wiring and the ground wiring, wherein at least one electrode of the decoupling capacitor consists of a shield layer formed in a plane shape on a semiconductor substrate, and the shield layer is electrically connected directly to the semiconductor substrate and is fixed to a power supply potential or the ground potential.

    摘要翻译： 一种半导体集成电路，包括电源布线和接地布线以及形成在电源布线和接地布线之间的去耦电容器，其中去耦电容器的至少一个电极由在半导体上形成为平面形状的屏蔽层组成 衬底，并且屏蔽层直接电连接到半导体衬底并且被固定到电源电位或地电位。

    Balloon catheter
    5.
    发明授权
    Balloon catheter 有权
    气球导管

    公开(公告)号：US07172796B2

    公开(公告)日：2007-02-06

    申请号：US10632952

    申请日：2003-08-04

    申请人： Yasushi Kinoshita ,  Hiraku Murayama

    发明人： Yasushi Kinoshita ,  Hiraku Murayama

    IPC分类号： B29D22/00 ,  B29D23/00 ,  B32B1/08

    CPC分类号： A61L29/126 ,  Y10T428/1334 ,  Y10T428/1352 ,  Y10T428/1362 ,  Y10T428/1369

    摘要： A balloon catheter includes a long-sized body extending between a proximal end and a distal end, the body internally having at least one lumen, and a balloon made from a composite material composed of short-fibers for reienforcement and a matrix resin, the balloon being disposed on the distal side of the long-sized body. The short-fibers are oriented in the balloon in such a manner that in a longitudinal cross-section of the balloon, 25% or more of the short-fibers are oriented in the major-axis direction of the balloon, 25% or more of the short-fibers are oriented in the direction oblique to the major-axis direction, and the remaining short-fibers are oriented in the direction nearly perpendicular to the major-axis direction; and in a diametrical cross-section of the balloon, 8% or more of the short-fibers are oriented in the circumferential direction of the balloon, 25% or more of the short-fibers are oriented in the direction perpendicular to the circumferential direction, that is, in the major-axis direction, and the remaining short-fibers are oriented in the direction oblique to the circumferential direction. The balloon catheter exhibits a high strength to withstand pressure and a good trackability.

    摘要翻译： 气囊导管包括在近端和远端之间延伸的长尺寸的身体，身体内部具有至少一个内腔，以及由复合材料制成的气囊，用于再纤维的短纤维和基质树脂，气囊 设置在长型身体的远侧。 短纤维以这样的方式定向在气囊中：在气囊的纵向截面中，25％以上的短纤维在球囊的长轴方向上取向，25％以上的短纤维 短纤维在与长轴方向倾斜的方向上取向，剩余的短纤维在大致垂直于长轴方向的方向上取向; 并且在气囊的直径截面中，短纤维的8％以上在球囊的圆周方向上取向，短纤维的25％以上在与圆周方向垂直的方向上取向， 即在长轴方向上，剩余的短纤维在与圆周方向倾斜的方向上取向。 气囊导管具有高强度以承受压力和良好的追踪性。

    LSI test socket for BGA
    6.
    发明授权
    LSI test socket for BGA 失效
    用于BGA的LSI测试插座

    公开(公告)号：US07129728B2

    公开(公告)日：2006-10-31

    申请号：US10553189

    申请日：2004-07-09

    申请人： Yasushi Kinoshita

    发明人： Yasushi Kinoshita

    IPC分类号： G01R31/02

    CPC分类号： G01R1/0466 ,  G01R1/0483 ,  G01R1/06722

    摘要： There is provided an LSI socket containing a pogo-pin type decoupling capacitor for reducing the potential fluctuation of power supplies and GNDs at the time of testing LSI incorporated in a BGA package. The LSI socket comprises a printed board 102 containing decoupling capacitors 113 corresponding to one or more power supply voltages inside thereof, a pogo-pin supporting casing portion 104 on which the printed board 102 is overlapped into a single piece, and pogo-pins 103 inserted into penetrating holes in which hole positions of through holes 109 drilled in the printed board 102 and casing holes 114 drilled in the pogo-pin supporting casing portion 104 are allowed to be matched, wherein the printed board 102 is disposed on the upper surface side of the pogo-pin supporting casing portion 104 which faces the BGA package, or disposed on the lower surface side of the pogo-pin supporting casing portion 104, at the time of testing the LSI incorporated in the BGA package.

    摘要翻译： 提供了一种LSI插座，其包含用于在测试包含在BGA封装中的LSI时降低电源和GND的电位波动的pogo-pin型去耦电容器。 LSI插座包括：印刷电路板102，其包含对应于其内部的一个或多个电源电压的去耦电容器113;印刷电路板102重叠成单件的弹簧销支撑壳体部分104和插入的弹簧销103 能够匹配在印刷基板102上钻孔的贯通孔109的孔位置和在弹簧销支撑壳体部分104中钻出的壳体孔114的贯通孔，其中印刷基板102配置在 在测试包含在BGA封装中的LSI时，面向BGA封装的pogo-pin支撑壳体部分104或者布置在pogo-pin支撑壳体部分104的下表面侧上。

    Image forming apparatus
    7.
    发明授权
    Image forming apparatus 有权
    图像形成装置

    公开(公告)号：US06741830B2

    公开(公告)日：2004-05-25

    申请号：US10229056

    申请日：2002-08-28

    申请人： Yasushi Kinoshita ,  Kazutaka Sato ,  Shigeru Obata ,  Akitomo Kuwabara ,  Tetsuya Ooba

    发明人： Yasushi Kinoshita ,  Kazutaka Sato ,  Shigeru Obata ,  Akitomo Kuwabara ,  Tetsuya Ooba

    IPC分类号： G03G1500

    CPC分类号： G03G15/6517 ,  B41J15/005 ,  B41J15/046 ,  B41J15/16 ,  B65H23/038 ,  B65H23/048 ,  B65H2513/10 ,  B65H2513/51 ,  B65H2515/31 ,  G03G2215/00455 ,  B65H2220/02 ,  B65H2220/01

    摘要： When initially routing a continuous web along a path, the web walks across the width of the path, and uneven tension occurs causing the web to break in some cases when printing tension is applied thereto. Further, uneven web tension is produced on the right and left of the web by excessive walk control resulting from an excessive deviation of the web from the target position of a walk controller, with the result that the web is crumpled and broken. These problems are solved by maintaining a web tension that is lower than the printing tension until the web position converges on the target position of the walk controller after loading of the web, thereby reducing the amount of correction by the walk controller and the amount of web lost in the preparatory phase before printing, with the result that excellent image quality free from crumple or breakdown is ensured.

    摘要翻译： 当最初沿着路径布置连续卷材时，幅材横过路径的宽度，并且在打印张力被施加到其上的某些情况下，发生不均匀的张力，导致纸幅断裂。 此外，由于纸幅从步行控制器的目标位置的过度偏离导致的过度的步行控制，在幅材的右侧和左侧产生不均匀的幅材张力，结果是幅材被弄皱和破裂。 这些问题通过保持低于打印张力的卷筒纸张力来解决，直到卷筒纸位置在卷筒纸加载之后收敛到步行控制器的目标位置，从而减少了步行控制器的校正量和卷材的数量 在打印之前的准备阶段失去了效果，从而确保了没有褶皱或破裂的优异图像质量。

    Method for fabricating a semiconductor device with bipolar transistor
    8.
    发明授权
    Method for fabricating a semiconductor device with bipolar transistor 失效
    用双极晶体管制造半导体器件的方法

    公开(公告)号：US5843828A

    公开(公告)日：1998-12-01

    申请号：US593416

    申请日：1996-01-29

    申请人： Yasushi Kinoshita

    发明人： Yasushi Kinoshita

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/423 ,  H01L29/732 ,  H01L21/326

    CPC分类号： H01L29/66272 ,  H01L29/42304 ,  H01L29/732

    摘要： A semiconductor device with a bipolar transistor that enables to realize a reliable, electric connection of an intrinsic base region with a base electrode is provided. A semiconductor substructure has a surface area. An intrinsic base region is formed in the surface area. An emitter region is formed in the surface area to be surounded by the intrinsic base region, and an emitter electrode is formed to be contacted with the emitter region. An insulator is formed to surround the emitter electrode. A base electrode is formed not to be contacted with the intrinsic base region A conductive region is formed to be contacted with the intrinsic base region and the base electrode. The substructure has a recess formed on the surface area. The conductive region is produced by supplying a conductive material to the recess to be contacted with the intrinsic base region and the base electrode. The intrinsic base region is electrically connected to the base electrode through the conductive region. The recess is preferably produced by oxidizing a part of the surface area to form an oxide and removing the oxide.

    摘要翻译： 提供一种具有双极晶体管的半导体器件，其能够实现本征基极区域与基极的可靠的电连接。 半导体子结构具有表面积。 在表面积中形成本征基区。 在由本征基区域包围的表面区域中形成发射极区域，并且形成发射极电极以与发射极区域接触。 形成绝缘体以包围发射极电极。 基底电极形成为不与本征基极区域接触形成与本征基极区域和基极电极接触的导电区域。 该子结构具有形成在表面区域上的凹部。 通过向与本征基极区域和基极电极接触的凹部供给导电材料来制造导电区域。 本征基极区域通过导电区域与基极电连接。 该凹部优选通过氧化一部分表面积而形成氧化物并除去氧化物而制成。

    Method of manufacturing a complementary bipolar transistor
    9.
    发明授权
    Method of manufacturing a complementary bipolar transistor 失效
    制造互补双极晶体管的方法

    公开(公告)号：US5411898A

    公开(公告)日：1995-05-02

    申请号：US19898

    申请日：1993-02-19

    申请人： Yasushi Kinoshita ,  Kazuhito Niwano

    发明人： Yasushi Kinoshita ,  Kazuhito Niwano

    IPC分类号： H01L21/74 ,  H01L21/762 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/06 ,  H01L21/265

    CPC分类号： H01L21/82285 ,  H01L21/74 ,  H01L21/76229 ,  H01L21/76232 ,  H01L27/0826 ,  H01L29/0615 ,  Y10S148/01

    摘要： An n type buried layer (2b) lying in the lower part of a PNP transistor (101a) is lower in impurity concentration than an n.sup.+ type buried layer (2a) lying in the lower part of an NPN transistor (100). A p.sup.+ type buried layer (4a) is formed thick on the n type buried layer (2b) and insulated from the n.sup.+ type buried layer (2a) by an isolation trench (7). A breakdown voltage at a junction of the p.sup.+ type buried layer (4a) and the n type buried layer (2b) can be improved and, accordingly, the breakdown voltage of the whole device being improved. Low-controlled collector resistance of the PNP transistor (101a) prevents an amplification factor from decreasing.

    摘要翻译： 位于PNP晶体管（101a）的下部的n型掩埋层（2b）的杂质浓度低于位于NPN晶体管（100）的下部的n +型掩埋层（2a）。 在n型掩埋层（2b）上形成p +型掩埋层（4a），并通过隔离沟槽（7）与n +型掩埋层（2a）绝缘。 可以提高p +型掩埋层（4a）和n型掩埋层（2b）的结的击穿电压，从而提高整个器件的击穿电压。 PNP晶体管（101a）的低控制集电极电阻防止放大系数降低。