公开(公告)号：US07244679B2

公开(公告)日：2007-07-17

申请号：US10914994

申请日：2004-08-10

Applicant: Kwan-Ju Koh

Inventor： Kwan-Ju Koh

IPC: H01L21/311

CPC classification number: H01L21/28273 ,  B82Y10/00 ,  H01L29/42332

Abstract: Techiques for forming a silicon quantum dot, which can be applied to the formation of a semiconductor memory device, are disclosed. The techniques may include depositing a first dielectric layer on a semiconductor substrate, depositing a polysilicon layer on the first dielectric layer, forming a plurality of metal clusters on the polysilicon layer in regular distance, and etching the polysilicon layer using the plurality of metal clusters as a mask. As disclosed herein, it is possible to form the silicon quantum dots having the fineness and uniformity characteristic together with the single crystalline level characteristic.

Abstract translation: 公开了可用于形成半导体存储器件的用于形成硅量子点的技术。 所述技术可以包括在半导体衬底上沉积第一电介质层，在第一介电层上沉积多晶硅层，以规则的距离在多晶硅层上形成多个金属簇，并使用多个金属簇蚀刻多晶硅层作为 一个面具 如本文所公开的，可以形成具有细度和均匀性特性的硅量子点以及单晶等级特性。

公开(公告)号：US07049195B2

公开(公告)日：2006-05-23

申请号：US10749608

申请日：2003-12-30

Applicant: Kwan-Ju Koh

Inventor： Kwan-Ju Koh

IPC: H01L21/336

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  Y10S438/954

Abstract: The present disclosure is directed to a non-volatile memory device having a SONOS structure and a method of fabricating the same, wherein the non-volatile memory device having the SONOS structure is fabricated using a simple and lower cost method by greatly reducing the number of the photo engraving process. As disclosed herein, in one example a method of fabricating a non-volatile memory device includes forming a sacrificial oxide film on a semiconductor substrate and selectively etching the sacrificial oxide film to expose the semiconductor substrate with a predetermined width; injecting first conductive type impurity ions into the exposed semiconductor substrate to form a first semiconductor region, forming an additional oxide and nitride film on the entire upper surface of the semiconductor substrate in order; selectively etching the nitride film, the additional oxide, and the sacrificial oxide film to form a gate window which exposes the semiconductor substrate with a predetermined width; forming a gate oxide film over the entire upper surface of the semiconductor substrate; forming polysilicon layer on the gate oxide film to fill in the gate window; carrying out a CMP process until the sacrificial oxide film is exposed; removing the sacrificial oxide film, and the gate oxide film, the nitride film, and the additional oxide formed on the side wall of the polysilicon layer; injecting second conductive type impurity ions into portions of the semiconductor substrate, which corresponds to the outer part of the polysilicon layer, to form source and drain regions.

Abstract translation: 本公开涉及具有SONOS结构的非易失性存储器件及其制造方法，其中具有SONOS结构的非易失性存储器件使用简单且成本较低的方法制造，通过大大减少 照片雕刻过程。 如本文所公开的，在一个实例中，制造非易失性存储器件的方法包括在半导体衬底上形成牺牲氧化物膜，并选择性地蚀刻牺牲氧化物膜以以预定宽度露出半导体衬底; 将第一导电型杂质离子注入到暴露的半导体衬底中以形成第一半导体区域，在半导体衬底的整个上表面上依次形成附加的氧化物和氮化物膜; 选择性地蚀刻氮化物膜，附加氧化物和牺牲氧化膜以形成以预定宽度暴露半导体衬底的栅极窗口; 在半导体衬底的整个上表面上形成栅极氧化膜; 在栅极氧化膜上形成多晶硅层以填充栅极窗口; 进行CMP工艺，直到牺牲氧化膜暴露; 去除所述牺牲氧化膜，以及形成在所述多晶硅层的侧壁上的所述栅极氧化膜，所述氮化物膜和所述附加氧化物; 将第二导电型杂质离子注入到与多晶硅层的外部对应的半导体衬底的部分中以形成源区和漏区。

公开(公告)号：US07042062B2

公开(公告)日：2006-05-09

申请号：US11027034

申请日：2004-12-30

Applicant: Kwan-Ju Koh

Inventor： Kwan-Ju Koh

IPC: H01L21/762

CPC classification number: H01L21/76232

Abstract: A device isolation structure of a semiconductor device may be a silicon wafer, a trench formed in the silicon wafer to have a predetermined depth, a first thermal oxide layer formed to an inner surface of the trench, a pad oxide layer formed on the silicon wafer, a second thermal oxide layer formed on the pad oxide layer and having a round side adjacent to an opening of the trench, and a field oxide layer filled in the trench having the first thermal oxide layer.

Abstract translation: 半导体器件的器件隔离结构可以是硅晶片，形成在硅晶片中以具有预定深度的沟槽，形成在沟槽的内表面的第一热氧化物层，形成在硅晶片上的焊盘氧化物层 ，形成在所述焊盘氧化物层上并且具有与所述沟槽的开口相邻的圆形侧的第二热氧化物层和填充在具有所述第一热氧化物层的所述沟槽中的场氧化物层。

公开(公告)号：US20060094220A1

公开(公告)日：2006-05-04

申请号：US11257639

申请日：2005-10-25

Applicant: Kwan-Ju Koh

Inventor： Kwan-Ju Koh

IPC: H01L21/44

CPC classification number: H01L21/76877 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L2221/1089

Abstract: Methods of forming a metal line in a semiconductor device are disclosed. An illustrated method includes: depositing a first etch stop layer, an interlayer insulating layer, a second etch stop layer, and a line insulating layer on a semiconductor substrate; forming a contact hole pattern on the line insulating layer; forming a contact hole by etching an exposed portion of the interlayer insulating layer using the contact hole pattern as a mask; forming a trench pattern on the line insulating layer; forming a trench by etching an exposed portion of the line insulating layer using the trench pattern as a mask; removing exposed portions of the first etch stop layer and the second etch stop layer after forming the contact hole and the trench; forming a first metal thin film within the contact hole; and forming a second metal thin film on the first metal thin film.

Abstract translation: 公开了在半导体器件中形成金属线的方法。 所示方法包括：在半导体衬底上沉积第一蚀刻停止层，层间绝缘层，第二蚀刻停止层和线绝缘层; 在所述绝缘层上形成接触孔图案; 通过使用接触孔图案作为掩模蚀刻层间绝缘层的暴露部分来形成接触孔; 在所述绝缘层上形成沟槽图案; 通过使用沟槽图案作为掩模蚀刻线绝缘层的暴露部分来形成沟槽; 在形成接触孔和沟槽之后去除第一蚀刻停止层和第二蚀刻停止层的暴露部分; 在所述接触孔内形成第一金属薄膜; 以及在所述第一金属薄膜上形成第二金属薄膜。

公开(公告)号：US07033875B2

公开(公告)日：2006-04-25

申请号：US10911930

申请日：2004-08-04

Applicant: Kwan-Ju Koh

Inventor： Kwan-Ju Koh

IPC: H01L21/336

CPC classification number: H01L29/66651 ,  H01L29/7833 ,  H01L29/7834

Abstract: A MOS transistor and a method for fabricating the MOS transistor. The present invention enables implementation of a stable semiconductor device that is capable of protecting against leakage current generation by improving the “LDD effect” and securing a large process margin by adjusting an “off” current. The method for fabricating a MOS transistor includes placing or arranging an epitaxial layer between a silicon wafer and a gate electrode, and forming three impurity regions, including a very low concentration impurity region, and a low concentration impurity region and a high concentration impurity region (source and drain region).

Abstract translation: MOS晶体管及其制造方法。 本发明能够实现稳定的半导体器件，其能够通过改善“LDD效应”并通过调整“截止”电流来确保大的工艺裕度来防止泄漏电流产生。 制造MOS晶体管的方法包括在硅晶片和栅电极之间设置或布置外延层，并且形成包括极低浓度杂质区和低浓度杂质区和高浓度杂质区的三个杂质区（ 源极和漏极区）。

公开(公告)号：US20050139876A1

公开(公告)日：2005-06-30

申请号：US11027358

申请日：2004-12-30

Applicant: Kwan-Ju Koh

Inventor： Kwan-Ju Koh

IPC: H01L21/335 ,  H01L21/336 ,  H01L29/10 ,  H01L21/00 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66651 ,  H01L29/1045 ,  H01L29/66492 ,  H01L29/66621

Abstract: Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a channel region formed in the semiconductor substrate and overlapping the gate, and LDD regions formed in the semiconductor substrate and at both sides of the gate, centering the gate. In addition, the example transistor includes source and drain regions formed under the LDD regions, offset regions formed in the semiconductor substrate and between the channel region and LDD regions, and gate spacers formed at both sidewalls of the gate.

Abstract translation: 公开了晶体管及其制造方法。 示例性晶体管包括分为器件隔离区域和器件有源区域的半导体衬底。 示例性晶体管包括形成在半导体衬底的有源区中的栅极绝缘膜，形成在栅极绝缘膜上的栅极，形成在半导体衬底中并与栅极重叠的沟道区和形成在半导体衬底中的LDD区 门的两边，以门为中心。 此外，示例性晶体管包括形成在LDD区下的源极和漏极区域，形成在半导体衬底中以及沟道区域和LDD区域之间的偏移区域，以及形成在栅极的两个侧壁处的栅极间隔区。

公开(公告)号：US20050035407A1

公开(公告)日：2005-02-17

申请号：US10917141

申请日：2004-08-12

Applicant: Kwan-Ju Koh

Inventor： Kwan-Ju Koh

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7834 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: As disclosed herein, a semiconductor device includes a gate and a silicon substrate having a field region and an active region. A gate dielectric layer formed on the upper surface of the active region of the silicon substrate and on a gate dielectric layer. The gate may include first and second sidewall dielectric layers sequentially formed on sidewalls of the gate, epitaxial silicon layers formed at both sides of the gate on the silicon substrate, first LDD regions formed in the silicon substrate below the second sidewall dielectric layers, second LDD regions formed at one sides of the first LDD regions below the epitaxial silicon layers, source/drain regions formed under the second LDD regions, and silicide layers formed on the gate and the source/drain regions.

Abstract translation: 如本文所公开的，半导体器件包括具有场区和有源区的栅极和硅衬底。 栅电介质层，其形成在硅衬底的有源区的上表面上和栅介电层上。 栅极可以包括顺序地形成在栅极的侧壁上的第一和第二侧壁电介质层，形成在硅衬底上的栅极的两侧的外延硅层，在第二侧壁电介质层下面的硅衬底中形成的第一LDD区，第二LDD 形成在外延硅层下面的第一LDD区域的一侧的区域，形成在第二LDD区域下方的源极/漏极区域，以及形成在栅极和源极/漏极区域上的硅化物层。

公开(公告)号：US20070111445A1

公开(公告)日：2007-05-17

申请号：US11650216

申请日：2007-01-03

Applicant: Kwan-Ju Koh

Inventor： Kwan-Ju Koh

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0466 ,  H01L27/115

Abstract: The present disclosure relates to a flash memory including a common source line having a predetermined width formed on a semiconductor substrate, a common source in the semiconductor substrate below the common source line, and a couple of floating gates having a predetermined width formed on both outer side walls of the common source line. The flash memory may also include a couple of tunneling oxide layers formed between the floating gate and the common source line, and between the floating gate and the semiconductor substrate, a couple of dielectric layers formed on each of the couple of floating gates, and a couple of control gates formed on each of the couple of dielectric layers. Further, the flash memory may include a couple of drains formed in the semiconductor substrate by injecting impurity ions in using the control gate and the common source line as a mask.

公开(公告)号：US07208384B2

公开(公告)日：2007-04-24

申请号：US11027358

申请日：2004-12-30

Applicant: Kwan-Ju Koh

Inventor： Kwan-Ju Koh

IPC: H01L21/336

CPC classification number: H01L29/66651 ,  H01L29/1045 ,  H01L29/66492 ,  H01L29/66621

Abstract: Transistors and manufacturing methods thereof are disclosed. An example transistor includes a semiconductor substrate divided into device isolation regions and a device active region. The example transistor includes a gate insulating film formed in the active region of the semiconductor substrate, a gate formed on the gate insulating film, a channel region formed in the semiconductor substrate and overlapping the gate, and LDD regions formed in the semiconductor substrate and at both sides of the gate, centering the gate. In addition, the example transistor includes source and drain regions formed under the LDD regions, offset regions formed in the semiconductor substrate and between the channel region and LDD regions, and gate spacers formed at both sidewalls of the gate.

Abstract translation: 公开了晶体管及其制造方法。 示例性晶体管包括分为器件隔离区域和器件有源区域的半导体衬底。 示例性晶体管包括形成在半导体衬底的有源区中的栅极绝缘膜，形成在栅极绝缘膜上的栅极，形成在半导体衬底中并与栅极重叠的沟道区和形成在半导体衬底中的LDD区 门的两边，以门为中心。 此外，示例性晶体管包括形成在LDD区下的源极和漏极区域，形成在半导体衬底中以及沟道区域和LDD区域之间的偏移区域，以及形成在栅极的两个侧壁处的栅极间隔区。

公开(公告)号：US07145192B2

公开(公告)日：2006-12-05

申请号：US11035481

申请日：2005-01-13

Applicant: Kwan-Ju Koh

Inventor： Kwan-Ju Koh

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/66666 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66772 ,  H01L29/78642 ,  H01L29/78648

Abstract: An object of the present invention is to provide a MOS transistor of a new structure and a method of manufacturing the same that is capable of easily fabricating a high integration density device by overcoming photolithography limitations. The object of the present invention is accomplished by a MOS transistor, including a semiconductor substrate having a projection in which the width of an upper portion thereof is larger than that of a lower portion thereof; an isolating layer formed in the middle of substrate of the projection; first and second drain regions formed within the surface of the substrate of the projection; first and second source regions formed within the surface of the substrate on both sides of the projection; a gate insulating layer formed on the entire surface of the substrate; and first and second gates formed on the gate insulating layer on both sides of the substrate of the projection.

Abstract translation: 本发明的目的是提供一种新的结构的MOS晶体管及其制造方法，其能够通过克服光刻限制而容易地制造高集成度的器件。 本发明的目的是通过一种MOS晶体管实现，该MOS晶体管包括具有其上部宽度大于其下部的宽度的突起的半导体衬底; 形成在所述突起的基板的中间的隔离层; 形成在突起的基板的表面内的第一和第二漏极区域; 形成在所述基板的所述表面的所述突起的两侧的第一和第二源极区域; 形成在所述基板的整个表面上的栅极绝缘层; 以及在突起的基板的两侧上的栅极绝缘层上形成的第一和第二栅极。