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    Methods of forming semiconductor device with self-aligned contact elements and the resulting devices
    2.
    发明授权
    Methods of forming semiconductor device with self-aligned contact elements and the resulting devices 有权
    用自对准接触元件形成半导体器件的方法和所得到的器件

    公开(公告)号：US08940633B2

    公开(公告)日：2015-01-27

    申请号：US13785403

    申请日：2013-03-05

    申请人： GLOBALFOUNDARIES Inc.

    发明人： Xiuyu Cai ,  Ruilong Xie ,  John A. Iacoponi

    IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L29/40 ,  H01L29/78

    CPC分类号： H01L29/401 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.

    摘要翻译： 一种方法公开了进行蚀刻工艺以在源极/漏极区域的至少一部分上方的绝缘材料层中形成接触开口，其中在蚀刻工艺完成之后，晶体管的栅极结构的一部分是 暴露的，在暴露的栅极结构上选择性地形成可氧化材料，将可氧化材料的至少一部分转化为氧化物材料，以及在导电耦合到源/漏区的接触开口中形成导电接触。 本文公开的新型晶体管器件包括位于晶体管的导电接触和栅极结构之间的氧化物材料，其中氧化物材料接触导电接触并接触栅极结构的外表面的一部分但不全部接触。

    FinFET fabrication method
    3.
    发明授权
    FinFET fabrication method 有权
    FinFET制造方法

    公开(公告)号：US09123772B2

    公开(公告)日：2015-09-01

    申请号：US14044533

    申请日：2013-10-02

    申请人： GLOBALFOUNDARIES Inc

    发明人： Xusheng Wu ,  Wanxun He ,  Hongliang Shen

    IPC分类号： H01L21/00 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L27/0886 ,  H01L21/0217 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

    摘要： Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

    摘要翻译： 本发明的实施例提供了一种用于制造鳍式场效应晶体管（finFET）的改进方法。 牺牲区域形成在半导体衬底上。 间隔件邻近牺牲区域的两侧形成。 翅片基于间隔件形成。 将一组间隔物作为假间隔物处理，并且在翅片形成之前被除去，留下用于在最终半导体结构上形成翅片的另一组间隔件。 最终半导体结构上的所有鳍都由牺牲材料的一侧上的间隔物形成。 这减少了散热片的宽度变化。

    Methods of forming a semiconductor device with low-k spacers and the resulting device
    5.
    发明授权
    Methods of forming a semiconductor device with low-k spacers and the resulting device 有权
    形成具有低k间隔物的半导体器件的方法和所得到的器件

    公开(公告)号：US09064948B2

    公开(公告)日：2015-06-23

    申请号：US13656794

    申请日：2012-10-22

    申请人： GLOBALFOUNDARIES Inc.

    发明人： Xiuyu Cai ,  Ruilong Xie ,  Xunyuan Zhang

    IPC分类号： H01L29/78 ,  H01L21/283 ,  H01L29/49 ,  H01L29/66 ,  H01L21/768 ,  H01L29/51

    CPC分类号： H01L29/4991 ,  H01L21/7682 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

    摘要： One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.

    摘要翻译： 本文公开的一种方法包括形成邻近牺牲栅极结构的至少一个牺牲侧壁间隔物，所述牺牲栅极结构形成在半导体衬底上方，去除牺牲栅极结构的至少一部分，从而限定由牺牲隔离物横向限定的栅极腔， 在栅极腔中形成替代栅极结构，去除牺牲隔离物，从而限定邻近置换栅极结构的间隔空腔，并在间隔空腔中形成低k隔离物。 本文公开的新型器件包括位于半导体衬底上方的栅极结构，其中栅极绝缘层具有相对于衬底的上表面基本上垂直取向的两个直立部分。 该装置还包括邻近栅极绝缘层的垂直取向的竖立部分的低k侧壁间隔件。

    Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions
    6.
    发明授权
    Methods of forming a semiconductor device while preventing or reducing loss of active area and/or isolation regions 有权
    在防止或减少有源区和/或隔离区的损失的同时形成半导体器件的方法

    公开(公告)号：US08765542B1

    公开(公告)日：2014-07-01

    申请号：US13765797

    申请日：2013-02-13

    申请人： GLOBALFOUNDARIES Inc.

    发明人： Joachim Patzer ,  Frank Seliger ,  Markus Lenski ,  Stephan Kronholz

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823864 ,  H01L21/823828

    摘要： One method disclosed includes forming a gate structure of a transistor above a surface of a semiconducting substrate, forming a sidewall spacer proximate the gate structure, forming a sacrificial layer of material above the protective cap layer, sidewall spacer and substrate, forming an OPL layer above the sacrificial layer, reducing a thickness of the OPL layer such that, after the reduction, an upper surface of the OPL layer is positioned at a level that is below a level of an upper surface of the protective cap layer, performing a first etching process to remove the sacrificial layer from above the protective cap layer to expose the protective cap layer for further processing, performing a second etching process to remove the protective cap layer and performing at least one process operation to remove at least one of the OPL layer or the sacrificial layer from above the surface of the substrate.

    摘要翻译： 公开的一种方法包括在半导体衬底的表面上形成晶体管的栅极结构，在栅极结构附近形成侧壁隔离物，在保护盖层，侧壁间隔物和衬底上形成牺牲层，形成上面的OPL层 所述牺牲层减小所述OPL层的厚度，使得在所述还原之后，所述OPL层的上表面位于所述保护盖层的上表面的水平以下的水平，进行第一蚀刻工艺 以从保护盖层上方去除牺牲层以暴露保护盖层以进行进一步处理，执行第二蚀刻工艺以移除保护盖层并执行至少一个处理操作以去除OPL层或 牺牲层从衬底的表面上方。

    Integrating optimal planar and three-dimensional semiconductor design layouts
    9.
    发明授权
    Integrating optimal planar and three-dimensional semiconductor design layouts 有权
    整合最优平面和三维半导体设计布局

    公开(公告)号：US08966423B2

    公开(公告)日：2015-02-24

    申请号：US13792946

    申请日：2013-03-11

    申请人： GLOBALFOUNDARIES Inc.

    发明人： Navneet Jain ,  Yunfei Deng ,  Mahbub Rashed ,  David Doman ,  Qi Xiang ,  Jongwook Kye

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  Y02T10/82

    摘要： An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.

    摘要翻译： 提供了将不同半导体技术优化并组合成单个图形数据系统的方法和装置。 实施例包括生成平面半导体布局设计，产生三维（例如，FinFET）半导体布局设计，以及将平面设计和FinFET设计组合在通用图形数据系统中。