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594 条记录 (耗时 0.024 秒)

    Noise detecting circuit and associated system and method
    1.
    发明授权
    Noise detecting circuit and associated system and method 有权

    公开(公告)号：US12132456B2

    公开(公告)日：2024-10-29

    申请号：US18357989

    申请日：2023-07-24

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Bei-Shing Lien ,  Jaw-Juinn Horng

    IPC分类号： H03F3/21 ,  H03F3/193 ,  H03F3/45

    CPC分类号： H03F3/45179 ,  H03F3/193 ,  H03F3/211 ,  H03F3/45475 ,  H03F2200/171 ,  H03F2200/372

    摘要： A noise detecting circuit including an amplifier circuit amplifying an input signal indicating a noise level of a circuit to be detected and output an amplified signal; a filtering circuit receiving and filtering the amplified signal and output a filtered signal; and a comparing circuit receiving and compare the filtered signal to a reference voltage and output an output signal; wherein the filtering circuit includes: an output terminal; and a first filter selectively coupled to the output terminal, including: a sub-output terminal; a switch selectively coupling the sub-output terminal to the output terminal; a resistor, wherein a terminal of the resistor is coupled to the amplifier circuit and another terminal of the resistor is coupled to the sub-output terminal; and a capacitor, wherein a terminal of the capacitor is coupled to the sub-output terminal and another terminal of the capacitor is coupled to a reference voltage source.

    Memory circuit and word line driver
    4.
    发明授权
    Memory circuit and word line driver 有权

    公开(公告)号：US12112796B2

    公开(公告)日：2024-10-08

    申请号：US17674139

    申请日：2022-02-17

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Zhi-Hao Chang ,  Wei-Jer Hsieh

    IPC分类号： G11C11/418 ,  G11C11/408 ,  G11C11/413 ,  G11C11/4096

    CPC分类号： G11C11/418 ,  G11C11/4085 ,  G11C11/413 ,  G11C11/4096

    摘要： The present disclosure provides a memory circuit. The memory circuit includes: a plurality of word lines, a word line driver, and a first conductive line. The word line driver is electrically connected to the word lines. The word line driver includes: a plurality of first electronic components and a plurality of second electronic components. The plurality of first electronic components each electrically connected to the corresponding word line. The plurality of second electronic components each having a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line and the corresponding first electronic component. The first conductive line is electrically connected to the second terminal of the second electronic components. The first conductive line has a length proportional to the number of the word lines.

    Power clamp device
    9.
    发明授权
    Power clamp device 有权

    公开(公告)号：US12068597B2

    公开(公告)日：2024-08-20

    申请号：US17810602

    申请日：2022-07-03

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Pin-Hsin Chang ,  Hsin-Yu Chen ,  Tzu-Heng Chang

    IPC分类号： H02H9/00 ,  H03K5/13 ,  H03K5/00

    CPC分类号： H02H9/005 ,  H03K5/13 ,  H03K2005/00195

    摘要： The present disclosure provides a power clamp device. The power clamp device includes a delay element, a first transistor, a second transistor, and a gate control circuit. The delay element has an input terminal and an output terminal. The first transistor has a gate electrically connected to the output terminal of the delay element. The second transistor has a source electrically connected to a drain of the first transistor. The gate control circuit has a first terminal electrically connected to the input terminal of the delay element, a second terminal electrically connected to the output terminal of the delay element, and a third terminal electrically connected to a gate of the second transistor.

    Integrated circuit, memory device and method of manufacturing the same
    10.
    发明授权
    Integrated circuit, memory device and method of manufacturing the same 有权

    公开(公告)号：US12063785B2

    公开(公告)日：2024-08-13

    申请号：US17462663

    申请日：2021-08-31

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： Kuo-Pin Chang ,  Chien Hung Liu ,  Chih-Wei Hung

    IPC分类号： H10B51/20 ,  H10B51/30

    CPC分类号： H10B51/20 ,  H10B51/30

    摘要： A memory cell, an integrated circuit and method of manufacturing the same are provided. The memory device includes a substrate, gate layers and insulating layers, an isolation column, a channel layer, a first conductive feature, a second conductive feature, a storage layer and a pair of isolation structures. The isolation column extends through the gate layers and the insulating layers along a first direction. The channel layer laterally covers the isolation column. The first conductive feature and second conductive feature extend along the first direction and adjacent to the isolation column. The storage layer is disposed between the gate layers and the channel layer. The pair of isolation structures extends along the first direction. The pair of isolation structures includes a first isolation structure disposed between the first conductive feature and the gate layers, and a second isolation structure disposed between the second conductive feature and the gate layers.