公开(公告)号：US11361141B2

公开(公告)日：2022-06-14

申请号：US16940256

申请日：2020-07-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsuan-Ming Huang ,  An Shun Teng ,  Mingni Chang ,  Ming-Yih Wang ,  Yinlung Lu

IPC: G06F30/398 ,  H01L49/02 ,  H01L23/522

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes receiving layout data representing information for manufacturing the semiconductor structure having a metal layer over a substrate. A first parasitic capacitance and a second parasitic capacitance are formed between the metal layer and the substrate. The method further includes determining a parasitic capacitance difference between a first region and a second region. The method further includes forming a dummy capacitor to minimize the parasitic capacitance difference. A system for manufacturing a semiconductor device is also provided.

公开(公告)号：US20220406707A1

公开(公告)日：2022-12-22

申请号：US17667636

申请日：2022-02-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mingni Chang ,  Hsuan-Ming Huang ,  Shiou-Fan Chen

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A method is provided for producing a semiconductor structure including at least one capacitor. The method includes: forming a first metal layer; forming a second metal layer; forming a third high resistance (HiR) layer interposed between the first metal layer and the second metal layer, wherein at least one of the first metal layer and the sconed metal layer at least partially overlap with the third HiR layer; and defining at least one of a first capacitor between the first metal layer and the third HiR layer and a second capacitor between the second metal layer and the third HiR layer. Suitably, the method is carried out subsequent to a front-end-of-line (FEOL) portion of a semiconductor fabrication process.

公开(公告)号：US20240387244A1

公开(公告)日：2024-11-21

申请号：US18787573

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mingni CHANG ,  Hsuan-Ming Huang

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure describes a structure with passivation layers with rounded corners and a method for forming such a structure. The method includes forming a first insulating layer on a substrate, where the substrate includes a first conductive structure. The method further includes forming an opening in the first insulating layer to expose the first conductive structure and forming a second conductive structure on the first insulating layer, where the second conductive structure is in contact with the first conductive structure through the opening. The method further includes removing a portion of the second conductive structure with a first etching condition, removing a portion of the first insulating layer with a second etching condition, different from the first etching condition, to form a rounded corner between a sidewall of the second conductive structure and a top surface of the first insulating layer, and depositing a second insulating layer on the first insulating layer and the second conductive structure.

公开(公告)号：US12131992B2

公开(公告)日：2024-10-29

申请号：US18489864

申请日：2023-10-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun-Wei Chang ,  Hsuan-Ming Huang ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Mingni Chang ,  Ming-Yih Wang

IPC: H01L23/522 ,  H01L21/66 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L22/14 ,  H01L23/53209

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

公开(公告)号：US11830806B2

公开(公告)日：2023-11-28

申请号：US17244783

申请日：2021-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun-Wei Chang ,  Hsuan-Ming Huang ,  Jian-Hong Lin ,  Ming-Hong Hsieh ,  Mingni Chang ,  Ming-Yih Wang

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/66 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76843 ,  H01L22/14 ,  H01L23/53209

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

公开(公告)号：US20250054855A1

公开(公告)日：2025-02-13

申请号：US18928455

申请日：2024-10-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mingni Chang ,  Hsuan-Ming Huang ,  Shiou-Fan Chen

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A method is provided for producing a semiconductor structure including at least one capacitor. The method includes: forming a first metal layer; forming a second metal layer; forming a third high resistance (HiR) layer interposed between the first metal layer and the second metal layer, wherein at least one of the first metal layer and the sconed metal layer at least partially overlap with the third HiR layer; and defining at least one of a first capacitor between the first metal layer and the third HiR layer and a second capacitor between the second metal layer and the third HiR layer. Suitably, the method is carried out subsequent to a front-end-of-line (FEOL) portion of a semiconductor fabrication process.

公开(公告)号：US12154849B2

公开(公告)日：2024-11-26

申请号：US17667636

申请日：2022-02-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mingni Chang ,  Hsuan-Ming Huang ,  Shiou-Fan Chen

IPC: H01L29/00 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A method is provided for producing a semiconductor structure including at least one capacitor. The method includes: forming a first metal layer; forming a second metal layer; forming a third high resistance (HiR) layer interposed between the first metal layer and the second metal layer, wherein at least one of the first metal layer and the sconed metal layer at least partially overlap with the third HiR layer; and defining at least one of a first capacitor between the first metal layer and the third HiR layer and a second capacitor between the second metal layer and the third HiR layer. Suitably, the method is carried out subsequent to a front-end-of-line (FEOL) portion of a semiconductor fabrication process.

公开(公告)号：US20240387355A1

公开(公告)日：2024-11-21

申请号：US18787312

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Mingni Chang ,  Hsuan-Ming Huang ,  Shiou-Fan Chen

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: A method is provided for producing a semiconductor structure including at least one capacitor. The method includes: forming a first metal layer; forming a second metal layer; forming a third high resistance (HiR) layer interposed between the first metal layer and the second metal layer, wherein at least one of the first metal layer and the second metal layer at least partially overlap with the third HiR layer; and defining at least one of a first capacitor between the first metal layer and the third HiR layer and a second capacitor between the second metal layer and the third HiR layer. Suitably, the method is carried out subsequent to a front-end-of-line (FEOL) portion of a semiconductor fabrication process.

公开(公告)号：US10726191B2

公开(公告)日：2020-07-28

申请号：US16245975

申请日：2019-01-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsuan-Ming Huang ,  An Shun Teng ,  Mingni Chang ,  Ming-Yih Wang ,  Yinlung Lu

IPC: G06F30/30 ,  H01L23/522 ,  G06F30/398 ,  H01L49/02

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method includes receiving layout data representing mask information for manufacturing a semiconductive substrate with a conductor over the semiconductive substrate. A first capacitor is formed between the conductor and the semiconductive substrate. The method further includes determining a capacitance difference between capacitances of the first capacitor and a neighboring capacitor. The method further includes forming a dummy capacitor to minimize the capacitance difference. A system for manufacturing a semiconductor device is also provided.