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公开(公告)号：US11978511B2
公开(公告)日：2024-05-07
申请号：US17581351
申请日：2022-01-21
Inventor： Yung-Huei Lee , Chun-Wei Chang , Jian-Hong Lin , Wen-Hsien Kuo , Pei-Chun Liao , Chih-Hung Nien
CPC classification number: G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C2013/0092
Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.
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公开(公告)号：US11972826B2
公开(公告)日：2024-04-30
申请号：US17370763
申请日：2021-07-08
Inventor： Yung-Huei Lee , Pei-Chun Liao , Jian-Hong Lin , Dawei Heh , WenHsien Kuo
CPC classification number: G11C29/4401 , G11C13/0004 , G11C13/0069 , G11C29/12005 , G11C29/38
Abstract: Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.
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公开(公告)号：US11924965B2
公开(公告)日：2024-03-05
申请号：US17728758
申请日：2022-04-25
Inventor： Chun-Wei Chang , Jian-Hong Lin , Shu-Yuan Ku , Wei-Cheng Liu , Yinlung Lu , Jun He
CPC classification number: H05K1/0242 , H05K1/0251 , H05K1/116 , H05K3/427 , H05K3/429 , H05K2201/0776
Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
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公开(公告)号：US20230009913A1
公开(公告)日：2023-01-12
申请号：US17370763
申请日：2021-07-08
Inventor： Yung-Huei Lee , Pei-Chun Liao , Jian-Hong Lin , Dawei Heh , WenHsien Kuo
Abstract: Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.
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公开(公告)号：US09941159B2
公开(公告)日：2018-04-10
申请号：US15255333
申请日：2016-09-02
Inventor： Jian-Hong Lin , Hsin-Chun Chang , Shiou-Fan Chen , Chwei-Ching Chiu , Yung-Huei Lee
IPC: H01L23/528 , H01L23/522 , H01L21/768 , G06F17/50
CPC classification number: H01L21/76879 , G06F17/5072 , G06F17/5077 , H01L21/76802 , H01L23/5226 , H01L23/528 , H01L27/0207
Abstract: A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a third opening in the insulating layer and filling the first opening, the second opening and the third opening with a conductive material. The first opening has a width and a length. The second opening has a width less than the length of the first opening, and is electrically connected to the first opening. The third opening has a width less than the width of the second opening, and is electrically connected to the second opening.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10283450B2
公开(公告)日：2019-05-07
申请号：US15672780
申请日：2017-08-09
Inventor： Jian-Hong Lin , Chwei-Ching Chiu , Yung-Huei Lee , Chien-Neng Liao , Yu-Lun Chueh , Tsung-Cheng Chan , Chun-Lung Huang
IPC: H01L23/48 , H01L23/528 , H01L23/532 , H01L21/288 , H01L21/768
Abstract: A method, for forming a semiconductor device structure, includes: forming a conductive structure over a substrate, wherein the conductive structure includes twin boundaries. The forming the conductive structure includes: manipulating process conditions so as to promote formation of the twin boundaries and yet control a density of the twin boundaries to be outside a range for which a portion of a curve is an asymptote of a constant value, the curve representing values of an atomic migration ratio corresponding to values of the density of the twin boundaries.
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公开(公告)号：US20140145194A1
公开(公告)日：2014-05-29
申请号：US14166686
申请日：2014-01-28
Inventor： Bi-Ling Lin , Jian-Hong Lin , Ming-Hong Hsieh , Lee-Der Chen , Jiaw-Ren Shih , Chwei-Ching Chiu
IPC: H01L23/525 , H01L21/66 , H01L23/522
CPC classification number: H01L23/5256 , G01R31/2853 , G01R31/2858 , G01R31/2884 , H01L22/34 , H01L23/522 , H01L2924/0002 , H01L2924/00
Abstract: Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.
Abstract translation: 公开了半导体器件组件和方法。 在一个实施例中，半导体器件部件包括具有第一表面，与第一表面相对的第二表面，第一端和与第一端相对的第二端的导电段。 第一通孔在第一端耦合到导电段的第二表面。 第二通孔在第二端处耦合到导电段的第一表面，并且第三通孔在第二端耦合到导电段的第二表面。
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公开(公告)号：US12131992B2
公开(公告)日：2024-10-29
申请号：US18489864
申请日：2023-10-19
Inventor： Chun-Wei Chang , Hsuan-Ming Huang , Jian-Hong Lin , Ming-Hong Hsieh , Mingni Chang , Ming-Yih Wang
IPC: H01L23/522 , H01L21/66 , H01L21/768 , H01L23/532
CPC classification number: H01L23/5226 , H01L21/76843 , H01L22/14 , H01L23/53209
Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.
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公开(公告)号：US11830806B2
公开(公告)日：2023-11-28
申请号：US17244783
申请日：2021-04-29
Inventor： Chun-Wei Chang , Hsuan-Ming Huang , Jian-Hong Lin , Ming-Hong Hsieh , Mingni Chang , Ming-Yih Wang
IPC: H01L23/522 , H01L23/532 , H01L21/66 , H01L21/768
CPC classification number: H01L23/5226 , H01L21/76843 , H01L22/14 , H01L23/53209
Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.
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10.发明授权公开(公告)号：US10475742B2
公开(公告)日：2019-11-12
申请号：US16205997
申请日：2018-11-30
Inventor： Jian-Hong Lin , Chwei-Ching Chiu , Yung-Huei Lee , Chien-Neng Liao , Yu-Lun Chueh , Tsung-Cheng Chan , Chun-Lung Huang
IPC: H01L23/48 , H01L23/528 , H01L23/532 , H01L21/288 , H01L21/768
Abstract: A method of forming a semiconductor device structure includes: forming a first conductive structure over a substrate, the first conductive structure including twin boundaries; and wherein the forming the first conductive structure includes manipulating process conditions so as to promote formation of the twin boundaries resulting in a promoted density of twin boundaries such that the first conductive structure has an increased failure current density (FCD) relative to a baseline FCD of an otherwise substantially corresponding second conductive structure which has an unpromoted density of twin boundaries, the unpromoted density being less than the promoted density and such that the first conductive structure has a resistance which is substantially the same as the second conductive structure.
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