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公开(公告)号：US12270852B2
公开(公告)日：2025-04-08
申请号：US18672047
申请日：2024-05-23
Inventor： Jun He , Yu-Ting Lin , Wei-Hsun Lin , Yung-Liang Kuo , Yinlung Lu
IPC: G01R31/28
Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations: energizing an integrated circuit (IC) on a wafer by raising a voltage of the IC to a first voltage level during a first period, and applying to the IC a stress signal including a first sequence and a second sequence during a second period subsequent to the first period, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level, wherein a duration of the first sequence is longer than that of the second sequence.
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公开(公告)号：US20240395666A1
公开(公告)日：2024-11-28
申请号：US18474606
申请日：2023-09-26
Inventor： Yao-Chun Chuang , Tsung-Yu Ke , Chang-Jung Hsueh , Min-Feng Ku , Jun He
IPC: H01L23/48 , H01L21/768 , H01L23/532
Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a metal line over a first substrate, a second substrate over the metal line, and a through-via penetrating through the second substrate and landing on the metal line. The through-via includes a copper fill having at least 85% (111) crystal orientation. The through-via includes a top portion with a first top width over a bottom portion with a second top width that is smaller than the first top width, and the top portion includes a first bulk portion over a first footing feature. The first bulk portion has first sidewalls, the first footing feature has second sidewalls, and the second sidewalls slant inwards from the first sidewalls to narrow the through-via from the first top width of the top portion to the second top width of the bottom portion.
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公开(公告)号：US12066484B2
公开(公告)日：2024-08-20
申请号：US18359906
申请日：2023-07-27
Inventor： Jun He , Yu-Ting Lin , Wei-Hsun Lin , Yung-Liang Kuo , Yinlung Lu
CPC classification number: G01R31/2879 , G01R31/2642 , G01R31/2886
Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
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公开(公告)号：US12025655B2
公开(公告)日：2024-07-02
申请号：US18301274
申请日：2023-04-17
Inventor： Jun He , Yu-Ting Lin , Wei-Hsun Lin , Yung-Liang Kuo , Yinlung Lu
IPC: G01R31/28
CPC classification number: G01R31/2879 , G01R31/2886
Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
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公开(公告)号：US11924965B2
公开(公告)日：2024-03-05
申请号：US17728758
申请日：2022-04-25
Inventor： Chun-Wei Chang , Jian-Hong Lin , Shu-Yuan Ku , Wei-Cheng Liu , Yinlung Lu , Jun He
CPC classification number: H05K1/0242 , H05K1/0251 , H05K1/116 , H05K3/427 , H05K3/429 , H05K2201/0776
Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
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Patent Agency Ranking
公开(公告)号：US20240030168A1
公开(公告)日：2024-01-25
申请号：US17814525
申请日：2022-07-24
Inventor： Wei-Yu Chen , Hua-Wei Tseng , Li-Hsien Huang , Yinlung Lu , Jun He
IPC: H01L23/00 , H01L25/065 , H01L23/48
CPC classification number: H01L24/08 , H01L24/94 , H01L24/80 , H01L25/0657 , H01L23/481 , H01L2225/06524 , H01L2225/06593 , H01L2924/35121 , H01L2924/30205 , H01L2224/08145 , H01L2224/80908 , H01L2224/80896 , H01L2224/80895 , H01L2224/8011
Abstract: A package structure is provided. The package structure includes a bottom die and a top die. The bottom die includes: a first active region surrounded by a first seal ring region; a first seal ring region including a bottom seal ring; and a first bonding layer disposed on a front side of the bottom die. The top die includes: a second active region surrounded by a second seal ring region; a second seal ring region including a top seal ring; and a second bonding layer disposed on a front side of the top die. The bottom die and the top die are bonded through hybrid bonding between the first bonding layer and the second bonding layer at an interface therebetween such that the bottom seal ring and the top seal ring are vertically aligned and are operable to form a continuous seal ring.
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公开(公告)号：US20240063099A1
公开(公告)日：2024-02-22
申请号：US17889122
申请日：2022-08-16
Inventor： Ting-Ting Kuo , Li-Hsien Huang , Tien-Chung Yang , Yao-Chun Chuang , Yinlung Lu , Jun He
IPC: H01L23/498 , H01L21/48 , H01L21/56
CPC classification number: H01L23/49822 , H01L23/49894 , H01L21/4857 , H01L21/56
Abstract: The present disclosure provides methods and structures to prevent cracks in redistribution layers. A redistribution structure according to the present disclosure includes a first polymer layer disposed over a silicon substrate, a first contact via disposed in the first polymer layer, a second polymer layer disposed over the first contact via, a first redistribution layer including a first conductive pad disposed on the second polymer layer and a second contact via extending through the second polymer layer to physical contact the first contact via, a third polymer layer disposed over the first redistribution layer, a second redistribution layer including a second conductive pad disposed on the third polymer layer and a plurality of third contact vias extending through the third polymer layer to physically contact the first conductive pad. The first conductive pad has at least one opening and the second conductive pad has at least one opening.
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公开(公告)号：US11754621B2
公开(公告)日：2023-09-12
申请号：US17809577
申请日：2022-06-29
Inventor： Jun He , Yu-Ting Lin , Wei-Hsun Lin , Yung-Liang Kuo , Yinlung Lu
CPC classification number: G01R31/2879 , G01R31/2642 , G01R31/2886
Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
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公开(公告)号：US20250133770A1
公开(公告)日：2025-04-24
申请号：US18581058
申请日：2024-02-19
Inventor： Sze Hang Poon , Jun He , Hsi-Yu Kuo
IPC: H01L29/417 , H01L21/768 , H01L23/522 , H01L23/528 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/786
Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, a method includes forming a first antenna coupled to a gate structure of a transistor, the first antenna comprising a first metal line, forming a second antenna coupled to a source/drain feature of the transistor, the second antenna comprising a second metal line, wherein the first metal line and the second metal line are disposed within a same metallization layer, forming a dielectric layer over the metallization layer, performing a plasma etching process to the dielectric layer, thereby forming first trenches exposing the first metal line and second trenches exposing the second metal line, respectively, wherein the first trenches and second trenches are formed in a chronological order, and forming first and second conductive vias in the first trenches and second trenches, respectively.
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公开(公告)号：US12170327B2
公开(公告)日：2024-12-17
申请号：US17398668
申请日：2021-08-10
Inventor： Ming-Te Chen , Hui-Ting Tsai , Jun He , Kuo-Feng Yu , Chun Hsiung Tsai
IPC: H01L29/66 , H01L21/02 , H01L21/8234 , H01L27/088 , H01L29/78
Abstract: A semiconductor structure, a method for manufacturing a FinFET structure and a method for manufacturing a semiconductor structure are provided. The method for forming a FinFET structure includes: providing a FinFET precursor including a plurality of fins and a plurality of gate trenches between the fins; forming a first portion of the trench dummy of a dummy gate within the plurality of gate trenches; removing at least a part of the first portion of the trench dummy; forming a second portion of the trench dummy over the first portion of the trench dummy; performing a first thermal treatment to the first and second portions of the trench dummy; and forming a blanket dummy of the dummy gate over the second portion of the trench dummy. The present disclosure further provides a FinFET structure with an improved metal gate.
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