公开(公告)号：US11527655B2

公开(公告)日：2022-12-13

申请号：US17155467

申请日：2021-01-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Chieh Wang ,  Yu-Ting Lin ,  Yueh-Ching Pai ,  Shih-Chieh Chang ,  Huai-Tei Yang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/8234 ,  H01L21/02

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over a fin structure, and a source/drain (S/D) epitaxial layer formed in the fin structure and adjacent to the gate structure. The S/D epitaxial layer includes a first S/D epitaxial layer and a second epitaxial layer. The semiconductor structure includes a gate spacer formed on a sidewall surface of the gate structure, and the gate spacer is directly over the first S/D epitaxial layer. The semiconductor structure includes a dielectric spacer formed adjacent to the gate spacer, and the dielectric spacer is directly over the second epitaxial layer.

公开(公告)号：US20210080823A1

公开(公告)日：2021-03-18

申请号：US16573850

申请日：2019-09-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po Hsuan Li ,  Yu-Ting Lin ,  Yun-Yue Lin ,  Huai-Tei Yang

IPC: G03F1/62 ,  C23C14/32

Abstract: A pellicle comprises a stress-controlled metal layer. The stress in said metal layer may be between about 500-50 MPa. A method of manufacturing a pellicle comprising a metal layer includes deposing said metal layer by plasma physical vapor deposition. Process parameters are selected so as to produce a desired stress value in said metal layer, such as between about 500-50 MPa.

公开(公告)号：US10510851B2

公开(公告)日：2019-12-17

申请号：US15583570

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Wang ,  Yu-Ting Lin

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/263 ,  H01L21/261 ,  H01L21/265 ,  H01L29/78 ,  H01L21/02 ,  H01L29/45 ,  H01L21/322 ,  H01L21/768

Abstract: A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening.

公开(公告)号：US20150263109A1

公开(公告)日：2015-09-17

申请号：US14209374

申请日：2014-03-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Sheng-Wen Chen ,  Shih Yu-Shen ,  Chia Ping Lo ,  Yan-Hua Lin ,  Lun-Kuang Tan ,  Yu-Ting Lin

IPC: H01L29/417 ,  H01L21/285 ,  H01L29/16 ,  H01L29/45 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/324 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/41725 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L29/66575 ,  H01L29/7833

Abstract: A semiconductor device includes a transistor having a source/drain region. A conductive contact is disposed over the source/drain region. A silicide element is disposed below the conductive contact. The silicide element has a non-angular cross-sectional profile. In some embodiments, the silicide element may have an approximately curved cross-sectional profile, for example an ellipse-like profile. The silicide element is formed at least in part by forming an amorphous region in the source/drain region via an implantation process. The implantation process may be a cold implantation process.

Abstract translation: 半导体器件包括具有源极/漏极区域的晶体管。 在源极/漏极区域上设置导电接触。 硅化物元件设置在导电触点下方。 硅化物元件具有非角度横截面轮廓。 在一些实施例中，硅化物元件可以具有近似弯曲的横截面轮廓，例如椭圆形轮廓。 至少部分地通过经由注入工艺在源极/漏极区域中形成非晶区域来形成硅化物元件。 植入过程可以是冷植入过程。

公开(公告)号：US12265119B2

公开(公告)日：2025-04-01

申请号：US18192745

申请日：2023-03-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yi Chen ,  Kao-Chih Liu ,  Chia Hong Lin ,  Yu-Ting Lin ,  Min-Feng Ku

IPC: G01R31/28 ,  G01R1/04 ,  H01L23/522 ,  H01L23/00

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

公开(公告)号：US10157785B2

公开(公告)日：2018-12-18

申请号：US15583789

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Ching-Hwanq Su ,  Liang-Yueh Ou Yang ,  Ming-Hsing Tsai ,  Yu-Ting Lin

IPC: H01L21/768 ,  H01L21/288 ,  H01L29/66 ,  H01L23/532

Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.

公开(公告)号：US10153203B2

公开(公告)日：2018-12-11

申请号：US15665957

申请日：2017-08-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Wang ,  Yu-Ting Lin ,  Hung-Chang Hsu ,  Hsiao-Ping Liu ,  Hung Pin Lu ,  Yuan Wen Lin

IPC: H01L21/768 ,  H01L21/285

Abstract: A method includes forming an Inter-layer Dielectric (ILD) having a portion at a same level as a metal gate of a transistor. The ILD and the metal gate are parts of a wafer. The ILD is etched to form a contact opening. The wafer is placed into a PVD tool, with a metal target in the PVD tool. The metal target has a first spacing from a magnet over the metal target, and a second spacing from the wafer. A ratio of the first spacing to the second spacing is greater than about 0.02. A metal layer is deposited on the wafer, with the metal layer having a bottom portion in the contact opening, and a sidewall portion in the contact opening. An anneal is performed to react the bottom portion of the metal layer with the source/drain region to form a silicide region.

公开(公告)号：US20180315647A1

公开(公告)日：2018-11-01

申请号：US15583789

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Wang ,  Chi-Cheng Hung ,  Ching-Hwanq Su ,  Liang-Yueh Ou Yang ,  Ming-Hsing Tsai ,  Yu-Ting Lin

IPC: H01L21/768 ,  H01L21/288 ,  H01L29/66 ,  H01L23/532

CPC classification number: H01L21/76846 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/66795

Abstract: A method includes forming a first opening in a dielectric layer over a substrate, lining sidewalls and a bottom of the first opening with a conductive barrier layer, and depositing a seed layer over the conductive barrier layer. The method further includes treating the seed layer with a plasma process, and filling the first opening with a conductive material after the treating the seed layer.

公开(公告)号：US08680635B2

公开(公告)日：2014-03-25

申请号：US13728710

申请日：2012-12-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Uway Tseng ,  Lin-June Wu ,  Yu-Ting Lin

IPC: H01L31/0232

CPC classification number: H01L27/14636 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L27/1464 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.

Abstract translation: 集成电路包括具有焊盘区域和非接合焊盘区域的衬底。 在接合区域中的基板上形成了称为“大通孔”的较大通孔。 大通孔在朝向基板的顶视图中具有第一尺寸。 集成电路还包括在非接合区域中形成在衬底上的多个通孔。 多个通孔各自在顶视图中具有第二尺寸，第二尺寸基本上小于第一尺寸。

公开(公告)号：US12300729B2

公开(公告)日：2025-05-13

申请号：US16715927

申请日：2019-12-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Wang ,  Yu-Ting Lin

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/261 ,  H01L21/263 ,  H01L21/285 ,  H01L21/322 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

Abstract: A device includes a metal-silicide region formed in a semiconductor material in a contact opening. A concentration of a material, including chlorine, fluorine, or a combination thereof is in the metal-silicide region near an uppermost surface of the metal-silicide region. The presence of chlorine or fluorine results from a physical bombarding of the chlorine or fluorine in the contact opening. As a result of the physical bombard, the opening becomes wider at the bottom of the opening and the sidewalls of the opening are thinned. A capping layer is over the metal-silicide region and over sidewalls of a contact plug opening. A contact plug is formed over the capping layer, filling the contact plug opening. Before the contact plug is formed, a silicidation occurs to form the metal-silicide and the metal-silicide is wider than the bottom of the opening.