公开(公告)号：US20250048763A1

公开(公告)日：2025-02-06

申请号：US18921060

申请日：2024-10-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Lin Chen ,  Yi-Shin Chu ,  Yin-Kai Liao ,  Sin-Yi Jiang ,  Kuan-Chieh Huang ,  Jhy-Jyi Sze

IPC: H01L27/146 ,  H01L31/105

Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

公开(公告)号：US12205868B2

公开(公告)日：2025-01-21

申请号：US18355463

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.

公开(公告)号：US11901393B2

公开(公告)日：2024-02-13

申请号：US17184965

申请日：2021-02-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jhy-Jyi Sze ,  Sin-Yi Jiang ,  Yi-Shin Chu ,  Yin-Kai Liao ,  Hsiang-Lin Chen ,  Kuan-Chieh Huang ,  Jung-I Lin

IPC: H01L27/146 ,  G01S7/481

CPC classification number: H01L27/14649 ,  H01L27/1463 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14689 ,  H01L27/14698 ,  G01S7/4816

Abstract: The present disclosure provides a semiconductor structure, including a substrate including a first material, wherein the first material generates electrical signals from radiation within a first range of wavelengths, an image sensor element including a second material, wherein the second material generates electrical signals from radiation within a second range of wavelengths, the second range is different from first range, a transparent layer proximal to a light receiving surface of the image sensor element, wherein the transparent layer is transparent to radiation within the second range of wavelength, and an interconnect structure connected to a signal transmitting surface of the image sensor element.

公开(公告)号：US20230361005A1

公开(公告)日：2023-11-09

申请号：US18355463

申请日：2023-07-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L24/08 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2224/08145 ,  H01L2224/80895

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.

公开(公告)号：US20220302336A1

公开(公告)日：2022-09-22

申请号：US17383687

申请日：2021-07-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jhy-Jyi Sze ,  Sin-Yi Jiang ,  Yi-Shin Chu ,  Yin-Kai Liao ,  Hsiang-Lin Chen ,  Kuan-Chieh Huang

IPC: H01L31/112 ,  H01L31/18

Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed in a silicon substrate, in some embodiments, or on a silicon substrate, in some embodiments. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair doped region pair in the germanium layer is configured as an e-lens of the germanium-based sensor.

公开(公告)号：US11437708B2

公开(公告)日：2022-09-06

申请号：US17149853

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hsiang Huang ,  Fong-Yuan Chang ,  Tsui-Ping Wang ,  Yi-Shin Chu

IPC: H01Q1/22 ,  H01L23/66 ,  H01Q23/00 ,  H01Q1/50

Abstract: A 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

公开(公告)号：US11387167B2

公开(公告)日：2022-07-12

申请号：US16920430

申请日：2020-07-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Ching-Chun Wang ,  Kuan-Chieh Huang ,  Hsing-Chih Lin ,  Yi-Shin Chu

IPC: H01L23/52 ,  H01L23/48 ,  H01L21/48 ,  H01L21/02 ,  H01L23/522 ,  H01L21/768

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor substrate, a first metal layer, and a through substrate via (TSV). The semiconductor substrate has an active side. The first metal layer is closest to the active side of the semiconductor substrate, and the first metal layer has a first continuous metal feature. The TSV is extending from the semiconductor substrate to the first continuous metal feature. A width of the TSV at the first metal layer is wider than a width of the first continuous metal feature. Present disclosure also provides a method for manufacturing the semiconductor structure described herein.

公开(公告)号：US20190013345A1

公开(公告)日：2019-01-10

申请号：US16113819

申请日：2018-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Hsun Wan ,  Yi-Shin Chu ,  Szu-Ying Chen ,  Pao-Tung Chen ,  Jen-Cheng Liu ,  Dun-Nian Yaung

IPC: H01L27/146 ,  H04N5/378 ,  H01L31/0376 ,  H01L31/0352 ,  H01L31/0224 ,  H01L31/18

CPC classification number: H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/1463 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14685 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/1469 ,  H01L31/022466 ,  H01L31/035218 ,  H01L31/03762 ,  H01L31/18 ,  H04N5/378

Abstract: A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.

公开(公告)号：US12218106B2

公开(公告)日：2025-02-04

申请号：US18358186

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Hsing-Chih Lin ,  Jen-Cheng Liu ,  Yi-Shin Chu ,  Ping-Tzu Chen ,  Che-Wei Chen

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

公开(公告)号：US20250015102A1

公开(公告)日：2025-01-09

申请号：US18346544

申请日：2023-07-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Lin Chen ,  Yi-Shin Chu ,  Yin-Kai Liao ,  Sin-Yi Jiang ,  Sung-Wen Huang Chen

IPC: H01L27/146

Abstract: Some embodiments relate to an integrated circuit light sensor device. The integrated circuit light sensor device includes a semiconductor substrate, as well as a plurality of first light-absorption regions and a plurality of second light-absorption regions located in the semiconductor substrate. Each of the first light-absorption regions includes an implantation region of the semiconductor substrate. The implantation region and the semiconductor substrate form at least a portion of a corresponding one of a plurality of first photodetectors for a first light wavelength band. Each of the second light-absorption regions includes a semiconductor material different from the semiconductor substrate. The semiconductor material forms at least a portion of a corresponding one of a plurality of second photodetectors for a second light wavelength band different from the first light wavelength band.