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    Nonvolatile semiconductor memory
    81.
    发明申请
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US20050207220A1

    公开(公告)日：2005-09-22

    申请号：US10898377

    申请日：2004-07-26

    Applicant: Ken Takeuchi

    Inventor： Ken Takeuchi

    IPC: G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  H01L27/115 ,  H01L29/78

    CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5642 ,  H01L27/115

    Abstract: A nonvolatile semiconductor memory according to an example of the present invention comprises a memory cell array composed of a plurality of memory cells, an internal circuit which writes into the plurality of memory cells by use of one of a first mode in which a first threshold distribution can be obtained and a second mode in which a second threshold distribution different from the first threshold distribution can be obtained, and a threshold distribution control circuit which controls switchover between the first mode and the second mode.

    Abstract translation: 根据本发明的示例的非易失性半导体存储器包括由多个存储单元组成的存储单元阵列，内部电路通过使用第一模式中的一个来写入多个存储单元，其中第一模式 以及可以获得不同于第一阈值分布的第二阈值分布的第二模式，以及控制第一模式和第二模式之间的切换的阈值分配控制电路。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    82.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
    非易失性半导体存储器件

    公开(公告)号：US20050201156A1

    公开(公告)日：2005-09-15

    申请号：US10874361

    申请日：2004-06-24

    Applicant: Naoya Tokiwa

    Inventor： Naoya Tokiwa

    IPC: G11C16/02 ,  G11C16/06

    CPC classification number: G11C16/22

    Abstract: A nonvolatile semiconductor memory device with a function of executing a verify operation for write data that is input from outside includes a memory cell array including memory cells arranged in a matrix, and a password storage area for storing password data, an input buffer that receives data input from outside, a first retaining circuit that retains input password data or write data, which is input to the input buffer, a verify sense amplifier that detects, at a time of the verify operation, the password data that is read out of the password storage area or data that is read out of the memory cell array, and a coincidence determination circuit that determines whether the input password data coincides with the read-out password data, or determines whether the write data coincides with the read-out data.

    Abstract translation: 具有执行从外部输入的写入数据的验证操作的功能的非易失性半导体存储器件包括：存储单元阵列，包括以矩阵形式排列的存储单元;以及用于存储密码数据的密码存储区域;接收数据的输入缓冲器 来自外部的输入，保持输入到输入缓冲器的输入密码数据或写入数据的第一保持电路，在验证操作时检测从密码读出的密码数据的验证读出放大器 存储区域或从存储单元阵列读出的数据，以及一致确定电路，其确定输入的密码数据是否与读出的密码数据一致，或者确定写入数据是否与读出的数据一致。

    Semiconductor memory device and storage method thereof
    84.
    发明授权
    Semiconductor memory device and storage method thereof 有权
    半导体存储器件及其存储方法

    公开(公告)号：US06944055B2

    公开(公告)日：2005-09-13

    申请号：US10762827

    申请日：2004-01-21

    Applicant: Noboru Shibata ,  Tomoharu Tanaka

    Inventor： Noboru Shibata ,  Tomoharu Tanaka

    IPC: G11C16/02 ,  G11C7/00 ,  G11C11/56 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5642

    Abstract: For a verify operation using potential Vbi′, the data of a memory cell is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi′. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading.

    Abstract translation: 对于使用电位Vbi'的验证操作，通过使用电位Vai + 1预先读取存储单元的数据，并将存储单元的状态存储在锁存电路中。 然后，通过使用电位Vbi'进行验证/读取操作。 如果单元的状态高于Ai + 1，则验证/读取操作的结果被强制降低到低水平。 因此，只需要两个锁存电路来存储n位数据，包括一个用于存储要写入的数据的数据，一个用于在小区的状态高于Ai + 1时预先读取，并且存储 初步阅读。

    Channel erase type nonvolatile semiconductor memory device and electronic card and electronic apparatus using the device
    88.
    发明授权
    Channel erase type nonvolatile semiconductor memory device and electronic card and electronic apparatus using the device 有权
    通道擦除型非易失性半导体存储器件和使用该器件的电子卡和电子设备

    公开(公告)号：US06940754B2

    公开(公告)日：2005-09-06

    申请号：US10701159

    申请日：2003-11-04

    Applicant: Akira Umezawa

    Inventor： Akira Umezawa

    IPC: G11C16/02 ,  G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: G11C16/08 ,  G11C16/16 ,  G11C29/82

    Abstract: A channel erase flash memory including a redundancy word line group constituted of a plurality of redundancy word lines separately from a normal memory space of a memory cell array, and including a function of replacing the normal word line group including a defective memory cell with the redundancy word line group. In the memory, at the time of an erase operation, a first voltage is applied to a well region in which the memory cell array is formed, a second voltage of 0 V or less is applied to a normal word line, and a third voltage is applied to all the word lines included in the normal word line group including the defective memory cell or the redundancy word line group. A potential difference between the first and third voltages is set to be smaller than that between the first and second voltages.

    Abstract translation: 一种通道擦除闪速存储器，包括与存储单元阵列的正常存储器空间分开的多个冗余字线构成的冗余字线组，并且包括用包括具有冗余的缺陷存储器单元的正常字线组替换的功能 字线组。 在存储器中，在擦除操作时，对形成存储单元阵列的阱区域施加第一电压，对正常字线施加0V以下的第二电压，第三电压 被应用于包括有缺陷存储单元或冗余字线组的通常字线组中包括的所有字线。 第一和第三电压之间的电位差被设定为小于第一和第二电压之间的电位差。

    Nonvolatile semiconductor memory device having a write control circuit
    90.
    发明授权
    Nonvolatile semiconductor memory device having a write control circuit 有权
    具有写入控制电路的非易失性半导体存储器件

    公开(公告)号：US06937524B2

    公开(公告)日：2005-08-30

    申请号：US10461995

    申请日：2003-06-11

    Applicant: Hitoshi Shiga ,  Naoya Tokiwa

    Inventor： Hitoshi Shiga ,  Naoya Tokiwa

    IPC: G11C16/02 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C16/16 ,  G11C16/3436 ,  G11C2216/14

    Abstract: A non-volatile semiconductor memory device capable of performing page programming at high speeds is provided. This nonvolatile memory device includes a cell array with a matrix of rows and columns of electrically writable and erasable nonvolatile memory cells, and a write control circuit which writes or “programs” one-page data into this cell array at a plurality of addresses within one page. The write control circuit is operable to iteratively perform iteration of a write operation for the plurality of addresses corresponding to one page and iteration of a verify-read operation of the plurality of addresses after writing until verify-read check is passed with respect to every address involved. Regarding an address or addresses with no cells to be written any more, the write control circuit skips the write operation and the after-write verify-read operation.

    Abstract translation: 提供能够高速执行页面编程的非易失性半导体存储器件。 这种非易失性存储器件包括具有电可写和可擦除非易失性存储单元的行和列的矩阵的单元阵列，以及一个写入控制电路，其在一个位置内的多个地址中将一页数据写入或“编程”到该单元阵列 页。 写入控制电路可操作以迭代地执行对应于一页的多个地址的写入操作和写入之后多个地址的验证读取操作的迭代，直到相对于每个地址通过验证读取检查 涉及。 关于不再写入单元的地址或地址，写入控制电路跳过写入操作和写入后验证读取操作。

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