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    SEMICONDUCTOR MEMORY
    1.
    发明申请
    SEMICONDUCTOR MEMORY 审中-公开

    公开(公告)号：US20190259458A1

    公开(公告)日：2019-08-22

    申请号：US16123162

    申请日：2018-09-06

    Applicant: Noboru SHIBATA ,  Hironori UCHIKAWA

    Inventor： Noboru SHIBATA ,  Hironori UCHIKAWA

    IPC: G11C16/26 ,  H01L27/11582 ,  H01L27/1157 ,  G11C7/08 ,  G11C8/14 ,  G11C16/08 ,  G11C16/10 ,  G11C16/04

    Abstract: According to one embodiment, a semiconductor memory includes a first memory cell array including a plurality of first memory cells; and a second memory cell array including a plurality of second memory cells. Each of threshold voltages of the first memory cells and the second memory cells is set to any of a first threshold voltage, a second threshold voltage higher than the first threshold voltage, and a third threshold voltage higher than the second threshold voltage. Data of three or more bits including a first bit, a second bit, and a third bit is stored using a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.

    Semiconductor memory device including a flag for selectively controlling erasing and writing of confidential information area
    2.
    发明授权
    Semiconductor memory device including a flag for selectively controlling erasing and writing of confidential information area 有权
    半导体存储器件包括用于选择性地控制机密信息区域的擦除和写入的标志

    公开(公告)号：US09256525B2

    公开(公告)日：2016-02-09

    申请号：US13690961

    申请日：2012-11-30

    Applicant: Toshihiro Suzuki ,  Noboru Shibata ,  Takahiro Shimizu

    Inventor： Toshihiro Suzuki ,  Noboru Shibata ,  Takahiro Shimizu

    IPC: G06F12/02 ,  G06F12/14 ,  G06F21/79

    CPC classification number: G06F12/0246 ,  G06F12/1433 ,  G06F21/79

    Abstract: A semiconductor memory device includes a memory which comprises a confidential information area storing confidential information and a flag. A controller reads the flag from the memory when instructed to erase or write data in the confidential information area, determines whether the flag is set, erases or writes data in the confidential information area when the flag is clear, and abandons a process requested by an erase or write instruction when the flag is set. An authenticator uses data in the confidential information area to execute an operation for authentication. A management information area may store management information for associated pages. The flag may include a bit string and a complementary bit string to improve reliability of the flag. The confidential information area may store dummy data when the memory is used for uses other than an application with an authentication function, so no problem arises using a normal controller.

    Abstract translation: 半导体存储器件包括存储机密信息区域和标志的存储器。 当指示擦除或写入机密信息区中的数据时，控制器从存储器中读取该标志，当该标志清除时，确定在机密信息区中是否设置，擦除或写入数据，并放弃由 设置标志时擦除或写入指令。 验证者使用机密信息区域中的数据来执行认证操作。 管理信息区域可以存储关联页面的管理信息。 标志可以包括位串和互补位串，以提高标志的可靠性。 当存储器被用于除具有认证功能的应用程序之外的使用时，机密信息区域可以存储虚拟数据，因此使用普通控制器不会出现问题。

    Multilevel nonvolatile semiconductor memory system
    5.
    发明授权
    Multilevel nonvolatile semiconductor memory system 有权
    多级非易失性半导体存储器系统

    公开(公告)号：US08605500B2

    公开(公告)日：2013-12-10

    申请号：US13050431

    申请日：2011-03-17

    Applicant: Naoki Kobayashi ,  Mitsuaki Honma ,  Noboru Shibata

    Inventor： Naoki Kobayashi ,  Mitsuaki Honma ,  Noboru Shibata

    IPC: G11C11/34

    CPC classification number: G11C11/5628

    Abstract: According to one embodiment, a system includes a memory, a controller which controls an operation of the memory in a data program, and data bus which connects the memory to the controller. The memory comprises a memory cell array with memory cells which have a bit assignment to 2x (x is an integer number of 3 or more) threshold distributions, each memory cell storing x bits, and a control circuit which controls the data program of x bits to the memory cells. The controller comprises a first step generating y bit (y is an integer number and y

    Abstract translation: 根据一个实施例，系统包括存储器，控制数据程序中的存储器的操作的控制器以及将存储器连接到控制器的数据总线。 存储器包括具有存储器单元的存储器单元阵列，其具有位分配为2x（x为3或更多的整数）阈值分布，每个存储单元存储x位，以及控制电路，其控制x位数据程序 到记忆体细胞。 控制器包括基于x位产生y位（y为整数和y

    Semiconductor memory device with improved ECC efficiency
    7.
    发明授权
    Semiconductor memory device with improved ECC efficiency 有权
    具有提高ECC效率的半导体存储器件

    公开(公告)号：US08406054B2

    公开(公告)日：2013-03-26

    申请号：US13351266

    申请日：2012-01-17

    Applicant: Noboru Shibata ,  Kazunori Kanebako

    Inventor： Noboru Shibata ,  Kazunori Kanebako

    IPC: G11C11/34

    CPC classification number: G11C16/0483 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C29/00 ,  G11C2211/5621

    Abstract: Memory cells store k bits of data (k is a natural number not less than 2) into a single cell. A number n of data storage circuits store externally supplied k bits of data to write data into the memory cells. A control circuit inputs the data on a first page, a second page, . . . , a k-th page to every h (h≦n) of the data storage circuits and then writes the data in the n data storage circuits into the memory cells.

    Abstract translation: 存储单元将k位数据（k是不小于2的自然数）存储到单个单元中。 数字n个数据存储电路存储外部提供的k位数据以将数据写入存储单元。 控制电路输入第一页，第二页上的数据。 。 。 ，第k页到数据存储电路的每个h（h＆nlE; n），然后将数据写入n个数据存储电路到存储单元中。

    SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE 有权
    可减少芯片尺寸的半导体存储器件

    公开(公告)号：US20130003461A1

    公开(公告)日：2013-01-03

    申请号：US13608713

    申请日：2012-09-10

    Applicant: Katsuaki ISOBE ,  Noboru Shibata ,  Toshiki Hisada

    Inventor： Katsuaki ISOBE ,  Noboru Shibata ,  Toshiki Hisada

    IPC: G11C16/14 ,  G11C16/04

    CPC classification number: G11C16/16 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/1095

    Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

    Abstract translation: 根据一个实施例，形成在衬底中的第一导电类型的第一阱。 第二导电类型的第二阱形成在第一阱中。 多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是 布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

    Semiconductor memory device capable of shortening erase time
    10.
    发明授权
    Semiconductor memory device capable of shortening erase time 有权
    能够缩短擦除时间的半导体存储器件

    公开(公告)号：US08335114B2

    公开(公告)日：2012-12-18

    申请号：US13162051

    申请日：2011-06-16

    Applicant: Noboru Shibata

    Inventor： Noboru Shibata

    IPC: G11C11/34

    CPC classification number: G11C16/3445 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26

    Abstract: In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage.

    Abstract translation: 在存储单元阵列中，连接到多个字线和多个位线的多个存储单元被布置成矩阵。 控制电路控制所述多个字线和所述多个位线的电位。 在擦除操作中，控制电路使用第一擦除电压同时擦除所述多个存储单元的n个存储单元（n为等于或大于2的自然数），执行使用 第一验证电平，找到超过第一验证电平的单元数k（k＆nlE; n），根据数k确定第二擦除电压，并使用第二擦除电压再次执行擦除操作。

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