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    Data input / output control device and semiconductor memory device system
    2.
    发明授权
    Data input / output control device and semiconductor memory device system 有权
    数据输入/输出控制装置和半导体存储器件系统

    公开(公告)号：US08677217B2

    公开(公告)日：2014-03-18

    申请号：US13087035

    申请日：2011-04-14

    Applicant: Ken Takeuchi ,  Shuhei Tanakamaru

    Inventor： Ken Takeuchi ,  Shuhei Tanakamaru

    IPC: G11C29/00

    CPC classification number: G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411

    Abstract: When detected number of errors data Nerror exceeds the upper limit number of errors Nmax, an error correction circuit of a memory controller stores twice as long data length as stored data length for execution Sdata as the data length for execution Sdata in a correction information memory unit, and code length Scref longer than the data length for execution Sdata and detectable more errors than the upper limit number of errors as the code length for execution Scode in the correction information memory unit 32 (step S100 and S110). The error correction circuit encodes input data using BCH code having the stored code length for execution Scode, stored encoded data in a semiconductor memory device, is input data stored in the semiconductor memory device, performs error correction for input data using BCH code, and decode error corrected data.

    Abstract translation: 当检测到的错误数据数Nerr超过上限误差Nmax时，存储器控制器的纠错电路存储与存储的数据长度相同的两倍长的数据长度作为执行Sdata的数据长度作为校正信息存储单元中的执行数据长度Sdata ，并且代码长度Scref比执行数据长度Sdata长，并且比校正信息存储单元32中执行代码长度的错误上限数目多（步骤S100和S110）可检测到的错误数。 错误校正电路使用具有用于执行Scode的存储代码长度的BCH码，使用半导体存储器件中存储的编码数据的半导体存储器件中存储的编码数据的BCH码对输入数据进行编码，使用BCH码对输入数据执行纠错，并且解码 纠错数据

    Data processing apparatus, control device and data storage device
    3.
    发明授权
    Data processing apparatus, control device and data storage device 有权
    数据处理装置，控制装置和数据存储装置

    公开(公告)号：US08635511B2

    公开(公告)日：2014-01-21

    申请号：US13205239

    申请日：2011-08-08

    Applicant: Ken Takeuchi ,  Mayumi Fukuda

    Inventor： Ken Takeuchi ,  Mayumi Fukuda

    IPC: G11C29/00

    CPC classification number: G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G11C11/005 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0069 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

    Abstract: When write data D is high rewritten data, a PC 10 controls a DRAM 24 to store the write data D (steps S100 and S110). When the write data D is not the high rewritten data, the PC 10 outputs an RRAM write request signal and the write data D to an SSD (step S100 and S120). A memory controller of the SSD input the RRAM write request signal controls the RRAM and an SRAM to store the write data D in the RRAM or the SRAM. This treatment enables data stored in the DRAM to be rewritten frequently. Therefore, the decrease of number of times of refresh operation of the DRAM and the decrease of power consumption are accomplished.

    Abstract translation: 当写入数据D是高重写数据时，PC 10控制DRAM24以存储写入数据D（步骤S100和S110）。 当写入数据D不是高重写数据时，PC 10将一个RRAM写入请求信号和写入数据D输出到一个SSD（步骤S100和S120）。 SSD的存储器控​​制器输入RRAM写入请求信号控制RRAM和SRAM以将写数据D存储在RRAM或SRAM中。 这种处理使得存储在DRAM中的数据能够被频繁地重写。 因此，可以实现DRAM的刷新操作次数的减少和功耗的降低。

    Nonvolatile Semiconductor Memory Device
    7.
    发明申请
    Nonvolatile Semiconductor Memory Device 有权
    非易失性半导体存储器件

    公开(公告)号：US20100226173A1

    公开(公告)日：2010-09-09

    申请号：US12781396

    申请日：2010-05-17

    Applicant: Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    Inventor： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

    IPC: G11C16/04

    CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

    Abstract: A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

    Abstract translation: NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

    Sense amplifier circuit in multi-level non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node
    10.
    发明授权
    Sense amplifier circuit in multi-level non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node 有权
    多级非易失性半导体存储器中的感测放大器电路，包括用于在感测节点处升高电位的升压电容器

    公开(公告)号：US07567463B2

    公开(公告)日：2009-07-28

    申请号：US12123157

    申请日：2008-05-19

    Applicant: Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    Inventor： Koji Hosono ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Kenichi Imamiya

    IPC: G11C11/34 ,  G11C16/06

    CPC classification number: G11C16/0483 ,  G11C5/145 ,  G11C7/1006 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5643

    Abstract: A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range. In the caching operation mode, data transfer between one of the memory cells selected in accordance with a first address and the first latch is performed while data transfer is performed between the second latch and input/output terminals in accordance with a second address with respect to one-bit two-level data to be stored in one of the memory cells.

    Abstract translation: 非易失性半导体器件具有存储单元阵列，其具有电可擦除可编程非易失性存储器单元，重新编程和检索电路，其临时存储要存储在存储单元阵列中的要编程的数据并感测从存储器单元阵列检索的数据。 每个重新编程和检索电路具有选择性地连接到存储单元阵列和传送数据的第一和第二锁存器。 控制器控制数据重新编程操作中的重新编程和检索电路以及来自存储单元阵列的数据检索操作。 每个重新编程和检索电路都具有多级逻辑操作模式和缓存操作模式。 在多级逻辑操作模式中，使用第一和第二锁存器来执行二位四电平数据的高位和低位的重新编程和检索，以将两位四电平数据存储在存储单元之一中 在预定的阈值电平范围内。 在高速缓存操作模式中，根据第一地址选择的存储器单元之一和第一锁存器之间的数据传输是在第二锁存器和输入/输出端子之间根据第二地址相对于 要存储在其中一个存储单元中的一位二电平数据。

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