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    Capacitor and method for manufacturing the same
    85.
    发明申请
    Capacitor and method for manufacturing the same 有权
    电容器及其制造方法

    公开(公告)号：US20050121772A1

    公开(公告)日：2005-06-09

    申请号：US11003784

    申请日：2004-12-06

    Applicant: Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

    Inventor： Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

    IPC: H01G4/12 ,  H01G4/30 ,  H01G4/40 ,  H01K1/16 ,  H01L21/44 ,  H01L23/48 ,  H05K1/14 ,  H05K1/16

    CPC classification number: H05K1/162 ,  H01G4/30 ,  H01G4/40 ,  H01L2924/0002 ,  H05K1/141 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/10674 ,  H05K2203/061 ,  Y10S257/924 ,  Y10S438/957 ,  Y10T29/435 ,  Y10T29/49155 ,  H01L2924/00

    Abstract: A multilayer ceramic capacitor (10) having reduced inductance which is separated into a first layer body (11) and a second layer body (12). The first layer body (11) and the second layer body (12) are formed by alternately layering inner electrodes (inner electrode 13a, inner electrode 13b) so as to face each other and sandwich ceramic layers (14). The ceramic layers (14) of the second layer body (12) are thicker than the ceramic layers (14) of the first layer body (11), so as to compensate for electrode height difference. Moreover, in the second layer body (12), the inner electrodes (13b) are electrically connected by via electrode (15b) so that the part of the via electrode (15b) extending without connection to an inner electrode (13b) is shortened.

    Abstract translation: 具有减小的电感的多层陶瓷电容器（10）被分离成第一层体（11）和第二层体（12）。 第一层体（11）和第二层体（12）通过交替层叠内部电极（内部电极13a，内部电极13b）以使其彼此面对并夹着陶瓷层（14）而形成。 第二层体（12）的陶瓷层（14）比第一层体（11）的陶瓷层（14）厚，以补偿电极的高度差。 此外，在第二层体（12）中，内部电极（13b）通过电极（15b）电连接，使得通孔电极（15b）的一部分不与内部电极（13b）连接 ）缩短。

    High speed electronics interconnect and method of manufacture
    87.
    发明申请
    High speed electronics interconnect and method of manufacture 有权

    公开(公告)号：US20040174223A1

    公开(公告)日：2004-09-09

    申请号：US10793362

    申请日：2004-03-04

    Inventor： Dutta Achyut

    IPC: H01P003/08

    CPC classification number: H01L23/66 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2223/6627 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/1903 ,  H01L2924/19032 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01P1/2005 ,  H01P3/08 ,  H05K1/0224 ,  H05K1/0236 ,  H05K1/024 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/0313 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09681 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/05599

    Abstract: Fundamental interconnect systems for connecting high-speed electronics elements are provided. Interconnect system has the means, which could reduce the microwave loss by reducing the effective dielectric loss and dielectric constant of the interconnect system, and increase the bandwidth of the interconnects and also reduce the signal propagation delay, respectively. Ideally, the speed of the electrical signal on the signal line can be reached to speed of the light in the air, and the bandwidth can be reached to closer to the optical fiber. The interconnect systems consists of the signal line, dielectric system with opened trench or slot filled up with the air or lower dielectric loss material, and the ground plan. The signal line proposed in this invention could be made any type of signal line configuration for example, microstripline, strip line or coplanar line. The signal line can also be made as single ended or differential pairs of any configurations. The interconnect system based on the fundamental techniques provided in this invention, can be used for on-chip interconnects where the high speed electronics devices are connected by the signal line laid on the oxide or dielectric material. Again, the interconnect system based on the fundamental techniques provided in this invention, can also be used for off-chip interconnects (chip-to-chip interconnects), where the whole portion or portion of the PCB on which high speed chips are to be connected, are having the dielectric system with opened trench or slot to reduce the microwave loss. High scale chip-to-chip interconnection using of the multilayered PCB is possible. The fundamental techniques provided in this invention can also be used for high-speed connectors and high-speed cables. The main advantages of this invention are to make high speed interconnects systems for on-chip and off-chip interconnects. More over, this fundamental technology is also used for the high sped die package, high speed connector, and high speed cables where conventional manufacturing technology can be used and yet to increase the bandwidth of the interconnects.

    Method for connecting electrical components
    88.
    发明授权
    Method for connecting electrical components 有权
    电气元件连接方法

    公开(公告)号：US06760969B2

    公开(公告)日：2004-07-13

    申请号：US09992031

    申请日：2001-11-26

    Applicant: Hiroyuki Kumakura

    Inventor： Hiroyuki Kumakura

    IPC: H05K330

    CPC classification number: H01R12/7076 ,  G02F1/13452 ,  H01R12/79 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/0191 ,  Y10T29/4913 ,  Y10T29/53174 ,  Y10T29/53178

    Abstract: A method for connecting electrical components is provided. The method includes electrically connecting electrodes on two separate substrates with an anisotropic electroconductive adhesive layer. The thickness of the electroconductive adhesive layer prior to connection (X) is given by: 0.5×{(A1C1+A2C2)/(B+C)}≦X≦2×{(A1C1+A2C2)/(B+C)} where: A1 is a height of electrodes on a first substrate, B1 is a width of the electrodes on the first substrate and C1 is a width of an interelectrode space between the electrodes on the first substrate; A2 is a height of electrodes on a second substrate, B2 is a width of the electrodes on the second substrate and C2 is a width of an interelectrode space between the electrodes on the second substrate; and B+C=B1+C1=B2+C2.

    Abstract translation: 提供了一种用于连接电气部件的方法。 该方法包括在两个单独的基板上用各向异性导电粘合剂层电连接电极。 连接前的导电粘合剂层的厚度（X）由下式给出：其中：A 1是第一衬底上的电极的高度，B 1是第一衬底上电极的宽度，C < 1>是第一基板上的电极之间的电极间空间的宽度; A 2是第二基板上的电极的高度，B 2是第二基板上的电极的宽度，C 2是第二基板上的电极之间的电极间空间的宽度; B + C = B 1 + C 1 = B 2 + C 2。

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