公开(公告)号：US20150140732A1

公开(公告)日：2015-05-21

申请号：US14578891

申请日：2014-12-22

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Mitsuhiro ICHIJO ,  Tetsuhiro TANAKA ,  Seiji YASUMOTO ,  Shun MASHIRO ,  Yoshiaki OIKAWA ,  Kenichi OKAZAKI

IPC分类号： H01L21/02 ,  H01L29/66

CPC分类号： H01L21/44 ,  C23C16/308 ,  C23C16/45578 ,  C23C16/511 ,  H01J37/32192 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/34 ,  H01L21/02274 ,  H01L21/0237 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/02631 ,  H01L21/67167 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/7869

摘要： It is an object to drive a semiconductor device at high speed or to improve the reliability of the semiconductor device. In a method for manufacturing the semiconductor device, in which a gate electrode is formed over a substrate with an insulating property, a gate insulating film is formed over the gate electrode, and an oxide semiconductor film is formed over the gate insulating film, the gate insulating film is formed by deposition treatment using high-density plasma. Accordingly, dangling bonds in the gate insulating film are reduced and the quality of the interface between the gate insulating film and the oxide semiconductor is improved.

摘要翻译： 本发明的目的是高速驱动半导体器件或提高半导体器件的可靠性。 在半导体器件的制造方法中，其中在绝缘性的衬底上形成栅电极，在栅电极上形成栅极绝缘膜，并且在栅极绝缘膜上形成氧化物半导体膜，栅极 通过使用高密度等离子体的沉积处理形成绝缘膜。 因此，栅极绝缘膜中的悬挂键减少，并且栅极绝缘膜和氧化物半导体之间的界面的质量得到改善。

公开(公告)号：US20150072490A1

公开(公告)日：2015-03-12

申请号：US14534088

申请日：2014-11-05

申请人： Intel Corporation

发明人： Brian S. DOYLE ,  Roza KOTLYAR ,  Uday SHAH ,  Charles C. KUO

IPC分类号： H01L29/66 ,  H01L21/02

CPC分类号： H01L29/7827 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02636 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  Y10S977/762

摘要： Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

摘要翻译： 垂直取向的纳米线晶体管包括具有在晶体管的长度上变化的组成的半导体层或栅电极。 在实施例中，晶体管沟道区域沿着沟道的长度成分地分级或分层以诱导应变，和/或包括高迁移率注入层。 在实施例中，沉积包括多个栅电极材料的栅极电极堆叠以沿着栅极长度调制栅电极功函数。

公开(公告)号：US20150060943A1

公开(公告)日：2015-03-05

申请号：US14470164

申请日：2014-08-27

申请人： Seoul Semiconductor Co., Ltd.

发明人： Takeya MOTONOBU ,  Kwan Hyun Lee ,  Eun Hee Kim

IPC分类号： H01L29/78 ,  H01L29/20 ,  H01L21/02 ,  H01L29/423 ,  H01L29/417 ,  H01L23/367 ,  H01L29/66 ,  H01L29/205

CPC分类号： H01L29/7827 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/02639 ,  H01L23/367 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/32 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66446 ,  H01L29/66666 ,  H01L29/7828 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating a nitride-based transistor includes sequentially forming a first nitride-based semiconductor layer doped with first type dopant, a second nitride-based semiconductor layer doped with at least one of a second type dopant, and a third nitride-based semiconductor layer doped with at least one of the first type dopants. A first trench is formed to penetrate the third and second nitride-based semiconductor layers and to extend into the first nitride-based semiconductor layer. A fourth nitride-based semiconductor layer doped with the first type dopants is formed to fill the first trench. A second trench is formed in the fourth nitride-based semiconductor layer. A gate electrode is formed in the second trench. A source electrode is formed to be electrically connected to at least one of the third and fourth nitride-based semiconductor layers, and a drain electrode is formed to be electrically connected to the first nitride-based semiconductor layer.

摘要翻译： 一种制造氮化物基晶体管的方法包括：顺序地形成掺杂有第一类型掺杂剂的第一氮化物基半导体层，掺杂有第二类型掺杂剂中的至少一种的第二氮化物基半导体层和第三氮化物基半导体 层中掺杂有至少一种第一类型掺杂剂。 形成第一沟槽以穿透第三和第二氮化物基半导体层并延伸到第一氮化物基半导体层中。 掺杂有第一类型掺杂剂的第四氮化物基半导体层被形成以填充第一沟槽。 在第四氮化物基半导体层中形成第二沟槽。 在第二沟槽中形成栅电极。 源电极形成为与第三氮化物类半导体层和第四氮化物系半导体层中的至少一方电连接，并且形成漏电极以与第一氮化物基半导体层电连接。

公开(公告)号：US20150050753A1

公开(公告)日：2015-02-19

申请号：US14461191

申请日：2014-08-15

申请人： Applied Materials, Inc.

发明人： Swaminathan T. SRINIVASAN ,  Atif M. NOORI ,  David K. CARLSON

IPC分类号： H01L21/66 ,  H01L21/02

CPC分类号： H01L21/02664 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/324 ,  H01L21/3245 ,  H01L21/67011 ,  H01L21/67098 ,  H01L21/67115 ,  H01L21/6719 ,  H01L21/67207 ,  H01L21/67248

摘要： Implementations of the present disclosure generally relate to methods and apparatus for forming a film on a substrate. More particularly, implementations of the present disclosure relate to methods and apparatus for heteroepitaxial growth of crystalline films. In one implementation, a method of heteroepitaxial deposition of a strain relaxed buffer (SRB) layer on a substrate is provided. The method comprises epitaxially depositing a buffer layer over a dissimilar substrate, rapidly heating the buffer layer to relax the buffer layer, rapidly cooling the buffer layer and determining whether the buffer layer has achieved a desired thickness.

摘要翻译： 本公开的实施方式一般涉及在基板上形成膜的方法和装置。 更具体地，本公开的实施方案涉及用于晶体膜的异质外延生长的方法和装置。 在一个实施方案中，提供了在衬底上的应变松弛缓冲层（SRB）层的异质外延沉积的方法。 该方法包括在不同的衬底上外延沉积缓冲层，快速加热缓冲层以使缓冲层松弛，快速冷却缓冲层，并确定缓冲层是否达到所需的厚度。

公开(公告)号：US20150014631A1

公开(公告)日：2015-01-15

申请号：US14378063

申请日：2013-02-12

申请人： QUNANO AB

发明人： Jonas Ohlsson ,  Mikael Bjork

IPC分类号： H01L21/02 ,  H01L29/778 ,  H01L21/306

CPC分类号： H01L21/0254 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02513 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30612 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0676 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/78642 ,  H01L29/78681 ,  H01L29/812 ,  H01L29/861 ,  H01L29/872

摘要： GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.

摘要翻译： GaN基纳米线用于生长具有用于制造各种半导体器件（例如用于电力电子器件的二极管和晶体管）的具有c面顶表面的高质量，谨慎的基底元件。

公开(公告)号：US20150004092A1

公开(公告)日：2015-01-01

申请号：US14489903

申请日：2014-09-18

申请人： Smoltek AB

发明人： Jonas T. Berg ,  Vincent Desmaris ,  Mohammad Shafiqul Kabir ,  Muhammad Amin Saleem ,  David Brud

IPC分类号： C01B31/02

CPC分类号： C23C16/26 ,  B82Y10/00 ,  B82Y40/00 ,  C01B32/15 ,  C23C16/503 ,  G02B6/26 ,  H01B13/0026 ,  H01L21/0237 ,  H01L21/02491 ,  H01L21/02521 ,  H01L21/02603 ,  H01L21/02606 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L21/4871 ,  H01L21/76802 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/3677 ,  H01L23/3737 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/53276 ,  H01L29/0665 ,  H01L29/66439 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for making one or more nanostructures is disclosed, the method comprising: depositing a conducting layer on an upper surface of a substrate; depositing a patterned layer of catalyst on the conducting layer; growing the one or more nanostructures on the layer of catalyst; and selectively removing the conducting layer between and around the one or more nanostructures. A device is also disclosed, comprising a substrate, wherein the substrate comprises one or more exposed metal islands separated by one or more insulating areas; a conducting helplayer disposed on the substrate covering at least some of the one or more exposed metal islands or insulating areas; a catalyst layer disposed on the conducting helplayer; and one or more nanostructures disposed on the catalyst layer.

公开(公告)号：US08916424B2

公开(公告)日：2014-12-23

申请号：US13755862

申请日：2013-01-31

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Atsuo Isobe ,  Kunio Hosoya

IPC分类号： H01L21/00 ,  H01L21/02

CPC分类号： H01L29/66969 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/0237 ,  H01L21/02565 ,  H01L21/383 ,  H01L21/425 ,  H01L21/441 ,  H01L21/47573 ,  H01L27/10873 ,  H01L27/1108 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/495 ,  H01L29/517 ,  H01L29/7869

摘要： To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film. After an oxide insulating film is formed over the oxide semiconductor film, a metal film may be formed over the oxide insulating film. Oxygen is added to the metal film to form a metal oxide film and added also to the oxide semiconductor film or the oxide insulating film.

摘要翻译： 为了提高包含氧化物半导体的晶体管的生产率，具有良好的电气特性。 在包括氧化物半导体膜上的栅绝缘膜和栅电极的顶栅晶体管中，在氧化物半导体膜上形成金属膜，向金属膜中添加氧以形成金属氧化物膜，并且金属氧化物 膜用作栅极绝缘膜。 在氧化物半导体膜上形成氧化物绝缘膜之后，可以在氧化物绝缘膜上形成金属膜。 向金属膜中添加氧以形成金属氧化物膜，并且还添加到氧化物半导体膜或氧化物绝缘膜。

公开(公告)号：US20140367676A1

公开(公告)日：2014-12-18

申请号：US14374250

申请日：2013-01-10

申请人： Merck Patent GmbH

发明人： Marc Haeming ,  Andreas Klyszcz ,  Klaus Bonrad ,  Peer Kirsch ,  Alexander Issanin ,  Daniel Walker

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/7869 ,  H01L21/0237 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02505 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02628 ,  H01L21/02664 ,  H01L29/66969

摘要： The invention relates to a process for the production of electrically semiconducting or conducting metal-oxide layers having improved conductivity which is suitable, in particular, for the production of flexible thin-film transistors, to metal-oxide layers produced thereby, and to the use thereof for the production of electronic components.

摘要翻译： 本发明涉及一种用于生产具有改进的导电性的电半导体或导电金属氧化物层的方法，该方法特别适用于制造柔性薄膜晶体管，由此制备的金属氧化物层，以及使用 用于生产电子元件。

公开(公告)号：US08912079B2

公开(公告)日：2014-12-16

申请号：US13266337

申请日：2010-04-28

申请人： Motoichi Ohtsu ,  Takashi Yatsui ,  Tadashi Kawazoe ,  Shunsuke Yamazaki ,  Koichi Kajiyama ,  Michinobu Mizumura ,  Keiichi Ito

发明人： Motoichi Ohtsu ,  Takashi Yatsui ,  Tadashi Kawazoe ,  Shunsuke Yamazaki ,  Koichi Kajiyama ,  Michinobu Mizumura ,  Keiichi Ito

IPC分类号： H01L21/20 ,  B05C9/08 ,  C23C16/48 ,  C23C16/30 ,  C30B25/00 ,  C30B29/40 ,  H01L21/02 ,  H01L33/00 ,  C23C14/54 ,  C23C16/52

CPC分类号： C23C16/481 ,  C23C14/548 ,  C23C16/303 ,  C23C16/52 ,  C30B25/00 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/0262 ,  H01L33/0062

摘要： Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate. In the compound semiconductor deposition method of depositing a compound semiconductor of a ternary or higher system on a substrate, propagation light of a smaller energy than a desired ideal excitation energy for the compound semiconductor is irradiated onto the substrate 13 while depositing the compound semiconductor on the substrate 13, near-field light is generated based on the irradiated propagation light from fine particles of the compound semiconductor deposited on the substrate 13, new vibrational levels for the compound semiconductor are formed in multiple stages based on the generated near-field light, and a component in the compound semiconductor corresponding to the excitation energy is excited with the propagation light through a vibrational level, among the new vibrational levels, which has an excitation energy equal to or smaller than the energy of the propagation light is excited to desorb the component.

摘要翻译： 提供一种在将化合物半导体沉积在基板上时以纳米级调节三元或更高系统的化合物半导体的发光波长的化合物半导体沉积方法。 在将三元或更高系统的化合物半导体沉积在衬底上的化合物半导体沉积方法中，将化合物半导体所需的理想激发能的能量较小的传播光照射到衬底13上，同时将化合物半导体沉积在 基板13，基于沉积在基板13上的化合物半导体的微粒的照射的传播光产生近场光，基于产生的近场光，以多个阶段形成化合物半导体的新的振动电平，以及 对应于激发能的化合物半导体中的成分被传播光激发，通过振动水平，激发能量等于或小于传播光的能量的新的振动水平被激发，从而解吸部件 。

公开(公告)号：US20140361308A1

公开(公告)日：2014-12-11

申请号：US14297464

申请日：2014-06-05

申请人： Sumitomo Electric Industries, Ltd.

发明人： Keiichi Yui ,  Ken Nakata ,  Tsuyoshi Kouchi ,  Isao Makabe

IPC分类号： H01L29/205 ,  H01L21/02

CPC分类号： H01L21/0254 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02414 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/66462 ,  H01L29/7786

摘要： A method of manufacturing a semiconductor device according to one aspect of the present invention includes a step of forming a first layer of InAlN, a step of forming a second layer of InAlGaN on the first layer under a growth temperature higher than that of the first layer, and a step of forming a third layer of GaN, AlGaN or InGaN under a growth temperature higher than that of the first layer.

摘要翻译： 根据本发明的一个方面的制造半导体器件的方法包括形成第一层InAlN的步骤，在第一层上在比第一层高的生长温度下形成第二层InAlGaN的步骤 以及在比第一层高的生长温度下形成第三层GaN，AlGaN或InGaN的步骤。