公开(公告)号：US06157578A

公开(公告)日：2000-12-05

申请号：US354398

申请日：1999-07-15

申请人： James Brady

发明人： James Brady

IPC分类号： G11C11/401 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/409 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/065 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

摘要： A device and method for accessing a row of data in a semiconductor memory device in a single operation is disclosed. The device includes a row of latches having a width which matches the width of the memory array in the semiconductor memory device. The device includes precharge and equilibration circuitry associated with the row of latches and the row of sense amplifiers in device, and timing circuitry for controlling the operation of each in performing full page read and write operations. Writing a full row of data from the row of latches into a selected row of memory cells includes the steps of disconnecting the row of sense amplifiers from the reference voltage sources; equalizing voltage levels appearing on the bit lines of the semiconductor memory and the sense amplifiers; connecting a row of memory cells to the bit lines; driving at least one bit line of each pair of bit lines to a voltage level representing the data value stored in the corresponding latch; coupling the sense amplifiers to the reference voltage sources for powering the sense amplifiers; and disconnecting the row of memory cells from the bit lines.

摘要翻译： 公开了一种用于在单个操作中访问半导体存储器件中的数据行的装置和方法。 该器件包括具有与半导体存储器件中的存储器阵列的宽度匹配的宽度的一排锁存器。 该装置包括与锁存器行和器件中的读出放大器行相关联的预充电和平衡电路，以及用于在执行全页读和写操作时控制每个操作的定时电路。 将锁存器行的全行数据写入选定行的存储单元包括以下步骤：将读出放大器行与参考电压源断开; 均衡出现在半导体存储器和读出放大器的位线上的电压电平; 将一行存储单元连接到位线; 将每对位线的至少一个位线驱动到表示存储在相应锁存器中的数据值的电压电平; 将读出放大器耦合到参考电压源以为读出放大器供电; 并将该行的存储单元从位线断开。

公开(公告)号：US6151273A

公开(公告)日：2000-11-21

申请号：US362667

申请日：1999-07-29

申请人： Hisashi Iwamoto ,  Takeshi Kajimoto

发明人： Hisashi Iwamoto ,  Takeshi Kajimoto

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C8/18 ,  G11C11/407 ,  G11C11/409 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C8/18 ,  G11C2207/229

摘要： A synchronous semiconductor memory device capable of improving substantial transfer rate is provided. In response to a write command immediately following an act command, a control signal generating circuit applies an inactive enable signal to a read preamplifier & write buffer. In response to a write command and a precharge command, the control signal generating circuit generates an active enable signal, and the read preamplifier & write buffer writes the data stored in an FIFO to a memory cell. As late write is not performed upon reception of a write command immediately following an act command, erroneous writing of data to a not intended address can be prevented.

摘要翻译： 提供了能够提高实质的传输速率的同步半导体存储器件。 响应于紧跟在动作命令之后的写入命令，控制信号产生电路将无效使能信号应用于读取的前置放大器和写入缓冲器。 响应于写入命令和预充电命令，控制信号产生电路产生有效使能信号，读取的前置放大器和写入缓冲器将存储在FIFO中的数据写入存储单元。 由于在接收到动作命令之后的写入命令时不执行后期写入，因此可以防止数据向不想要的地址的错误写入。

公开(公告)号：US6108243A

公开(公告)日：2000-08-22

申请号：US383014

申请日：1999-08-25

申请人： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

发明人： Takaaki Suzuki ,  Shinya Fujioka ,  Yasuharu Sato

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1072 ,  G11C2207/2281 ,  G11C2207/229

摘要： The present invention is an FCRAM comprising a first stage for performing command decoding, a second stage for performing sense amplifier activation, and a third stage for performing data input and output, configured in a pipeline structure, a plurality of data bits being transferred in parallel between the sense amplifiers and the third stage, wherein sense amplifiers are deactivated automatically and a reset operation is performed after data has been transferred in parallel between sense amplifiers and the third stage, in response to a standard read or write command.

摘要翻译： 本发明是一种FCRAM，包括用于执行命令解码的第一级，用于执行读出放大器激活的第二级，以及在流水线结构中执行数据输入和输出的第三级，并行传输的多个数据位 在读出放大器和第三级之间，其中读出放大器被自动去激活，并且在数据已经在感测放大器和第三级之间并行传送之后，响应于标准的读或写命令来执行复位操作。

公开(公告)号：US06064625A

公开(公告)日：2000-05-16

申请号：US1460

申请日：1997-12-31

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C29/84 ,  G11C7/1039 ,  G11C7/22 ,  G11C2207/229

摘要： The present invention internally latches a write data signal applied in synchronous with an external data strobe signal in response to an internal data strobe signal which is generated in response to this external data strobe signal, and furthermore, supplies the write data signal to a memory cell array from a write circuit such as a write amplifier in response to a write signal generated from this external data strobe signal. Meanwhile, an address signal is introduced internally in accordance with an external clock. Therefore, since the driving of the data bus connected to a memory cell array from a write amplifier, which constitutes a write operation internal to memory, commences in accordance with an external data strobe signal, a write operation can be ended in the shortest possible time from write data signal input. The above-described invention is especially effective when memory comprises a 2-bit pre-fetch. That is, a 2-bit write data signal is supplied time-sequentially in synchronous with an external data strobe signal. Since an internal write operation can commence after receiving for the input of that second write data signal, it enables the shortest write operation.

摘要翻译： 本发明响应于响应于该外部数据选通信号而产生的内部数据选通信号，内部锁存与外部数据选通信号同步施加的写入数据信号，此外，将写入数据信号提供给存储单元 响应于从该外部数据选通信号产生的写入信号，写入诸如写放大器的写入电路的阵列。 同时，根据外部时钟在内部引入地址信号。 因此，由于构成存储器内部的写操作的写放大器连接到存储单元阵列的数据总线的驱动根据外部数据选通信号开始，所以可以在最短的时间内结束写入操作 从写数据信号输入。 当存储器包括2位预取时，上述发明特别有效。 也就是说，与外部数据选通信号同步地按时间顺序地提供2位写入数据信号。 由于在接收到该第二写入数据信号的输入之后可以开始内部写入操作，所以能够进行最短的写入操作。

公开(公告)号：US11914888B2

公开(公告)日：2024-02-27

申请号：US17852165

申请日：2022-06-28

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC分类号： G06F3/06 ,  G06F13/16 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/065

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G11C7/06 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  H01L25/0657 ,  G06F2213/16 ,  G11C7/1015 ,  G11C2207/107 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L2225/06541

摘要： First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US11887658B2

公开(公告)日：2024-01-30

申请号：US17408603

申请日：2021-08-23

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Kangling Ji

IPC分类号： G11C7/10 ,  G11C11/4094 ,  G11C11/408 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096

CPC分类号： G11C11/4094 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/1087 ,  G11C2207/229

摘要： A data writing method and a memory, in which the data writing method is used for writing data to a memory array of the memory. The data writing method includes that: old data is read from a target column of the memory array; the old data is updated according to data to be written which carries target data bits information to generate new data; and the new data is written into the target column, in which the memory includes a plurality of data columns, the data is required to be written into the target column, and the target column includes a part of the data columns.

公开(公告)号：US11710527B2

公开(公告)日：2023-07-25

申请号：US17868685

申请日：2022-07-19

申请人： Micron Technology, Inc.

发明人： Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla ,  Peter Feeley ,  Sampath K. Ratnam ,  Sivagnanam Parthasarathy ,  Qisong Lin ,  Shane Nowell ,  Mustafa N. Kaynak

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C29/00 ,  G06F11/07 ,  G11C16/26 ,  G06F3/06 ,  G11C16/04

CPC分类号： G11C16/34 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/076 ,  G06F11/079 ,  G06F11/0793 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/84 ,  G11C16/0483 ,  G11C2207/229 ,  G11C2207/2272 ,  G11C2207/2281

摘要： A determination that a first programming operation has been performed on a particular memory cell can be made. A determination can be made, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate. In response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, an operation can be performed on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.

公开(公告)号：US20180166105A1

公开(公告)日：2018-06-14

申请号：US15688013

申请日：2017-08-28

申请人： Samsung Electronics Co., Ltd.

发明人： Il-han CHOI ,  Jae-jun Lee ,  Dong-yeop Kim ,  Kyu-dong Lee ,  Jeong-hyeon Cho

IPC分类号： G11C5/02

CPC分类号： G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C7/225 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L2224/16225

摘要： A memory module may include a first memory group and a second memory group; and a first clock signal line and a second clock signal line via which the first clock signal and the second clock signal propagate from the buffer chip to the first memory group and the second memory group, respectively, wherein distances that the first clock signals propagate from a buffer chip to a plurality of memory chips of the first memory group via the first clock signal line are identical to one another and are referred to as a first distance, and distances that the second clock signals propagate from the buffer chip to a plurality of memory chips of the second memory group via the second clock signal line are identical to one another and are referred to as a second distance.

公开(公告)号：US20180114550A1

公开(公告)日：2018-04-26

申请号：US15622157

申请日：2017-06-14

申请人： SK hynix Inc.

发明人： Yong-Deok CHO

IPC分类号： G11C7/04 ,  G11C7/22

CPC分类号： G11C7/04 ,  G11C7/1063 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2207/229

摘要： A memory system includes a memory device configured to store input data with a first time interval that is adjusted in response to a write command and a precharge command; and a controller configured to generate the write command and the precharge command, and to control the memory device, wherein the controller sets a change rate of the first time interval according to a temperature of the memory device, and adjusts a time interval between the write command and the precharge command on a basis of the set change rate and the temperature of the memory device.

公开(公告)号：US20170278563A1

公开(公告)日：2017-09-28

申请号：US15077636

申请日：2016-03-22

申请人： QUALCOMM Incorporated

发明人： Tony Chung Yiu KWOK ,  Changho JUNG

IPC分类号： G11C11/419

CPC分类号： G11C11/419 ,  G11C7/08 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/227 ,  G11C8/18 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory and a method for operating the memory are presented. The memory includes a memory cell, a sense amplifier configured to sense read data from the memory cell, a write driver configured to provide write data to the memory cell, a first circuit configured to enable the sense amplifier during a time period, and a second circuit configured to enable the write driver during at least a portion of the time period. The method includes enabling a sense amplifier to sense read data from a memory cell during a time period and enabling a write driver to provide write data to the memory cell during at least a portion of the time period. Another memory and method for operating the memory are presented. The memory and method further include an address input circuit configured to receive a write address while the sense amplifier is enabled.