公开(公告)号：US20170053944A1

公开(公告)日：2017-02-23

申请号：US15345495

申请日：2016-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/76202 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 提供了至少具有翅片结构的基板。 衬垫形成在翅片结构的侧壁上。 在翅片结构和基板之间形成氧化物层。 排除翅片结构，直到翅片结构的底层被保留，以在衬垫之间形成凹陷。 在凹部中依次形成缓冲外延层和外延层。 去除衬里的顶部，直到露出外延层的侧壁。 此外，还提供了通过所述方法形成的鳍状结构。

公开(公告)号：US20170040318A1

公开(公告)日：2017-02-09

申请号：US14842855

申请日：2015-09-02

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Chih-Kai Hsu ,  Chao-Hung Lin ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/45 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0649 ,  H01L29/45

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure on a first region and a second fin-shaped structure on a second region; forming a plurality of first gate structures on the first fin-shaped structure, a plurality of second gate structures on the second fin-shaped structure, and an interlayer dielectric (ILD) layer around the first gate structures and the second gate structures; forming a first patterned mask on the ILD layer; forming a second patterned mask on the second region; using the first patterned mask and the second patterned mask to remove all of the ILD layer from the first region and part of the ILD layer from the second region for forming a plurality of first contact holes in the first region and a plurality of second contact holes in the second region.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：在第一区域上提供具有第一鳍状结构的基底和在第二区域上提供第二鳍状结构; 在所述第一鳍状结构上形成多个第一栅极结构，在所述第二鳍状结构上形成多个第二栅极结构，以及围绕所述第一栅极结构和所述第二栅极结构的层间电介质（ILD）层; 在ILD层上形成第一图案化掩模; 在所述第二区域上形成第二图案化掩模; 使用第一图案化掩模和第二图案化掩模从第二区域从第一区域和ILD层的一部分去除所有ILD层，用于在第一区域中形成多个第一接触孔，以及多个第二接触孔 在第二个地区。

公开(公告)号：US20170018460A1

公开(公告)日：2017-01-19

申请号：US14825183

申请日：2015-08-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L23/535 ,  H01L29/78 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/0206 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/0226 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/535 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7856

Abstract: A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess.

Abstract translation: 制造具有自对准间隔物的半导体的方法包括提供衬底。 在基板上设置至少两个栅极结构。 暴露两个栅极结构之间的衬底。 形成氧化硅层以覆盖暴露的衬底。 含氮化物的材料层覆盖每个栅极结构和氧化硅层。 之后，对含氮化物的材料层进行蚀刻以在每个栅极结构的侧壁上形成第一自对准间隔物，并且暴露出部分氧化硅层，其中侧壁彼此相对。 然后，去除暴露的氧化硅层以形成第二自对准间隔物。 第一自对准间隔件和第二自对准间隔件协同地限定衬底上的凹部。 最后，在凹槽中形成接触塞。

公开(公告)号：US20160379839A1

公开(公告)日：2016-12-29

申请号：US14794821

申请日：2015-07-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L21/3105 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/785

Abstract: A method for making a semiconductor device. A substrate having a fin structure is provided. A continuous dummy gate line is formed on the substrate. The dummy gate line strides across the fin structure. A source/drain structure is formed on the fin structure on both sides of the dummy gate line. An interlayer dielectric (ILD) is formed on the dummy gate line and around the dummy gate line. The ILD is polished to reveal a top surface of the dummy gate line. After polishing the ILD, the dummy gate line is segmented into separate dummy gates.

Abstract translation: 一种制造半导体器件的方法。 提供具有翅片结构的基板。 在基板上形成连续的虚拟栅极线。 虚拟栅极线跨越翅片结构。 在虚拟栅极线的两侧的鳍结构上形成源极/漏极结构。 在虚拟栅极线上和虚拟栅极线周围形成层间电介质（ILD）。 ILD被抛光以露出虚拟栅极线的顶表面。 在抛光ILD之后，虚拟栅极线被分割成单独的虚拟栅极。

公开(公告)号：US09524987B2

公开(公告)日：2016-12-20

申请号：US14519146

申请日：2014-10-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/1211 ,  H01L21/76202 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-shaped structure includes the following steps. A substrate having at least a fin structure thereon is provided. A liner is formed on sidewalls of the fin structure. An oxide layer is formed between the fin structure and the substrate. The fin structure is removed until a bottom layer of the fin structure is reserved, to form a recess between the liner. A buffer epitaxial layer and an epitaxial layer are sequentially formed in the recess. A top part of the liner is removed until sidewalls of the epitaxial layer are exposed. Moreover, a fin-shaped structure formed by said method is also provided.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 提供了至少具有翅片结构的基板。 衬垫形成在翅片结构的侧壁上。 在翅片结构和基板之间形成氧化物层。 排除翅片结构，直到翅片结构的底层被保留，以在衬垫之间形成凹陷。 在凹部中依次形成缓冲外延层和外延层。 去除衬里的顶部，直到露出外延层的侧壁。 此外，还提供了通过所述方法形成的鳍状结构。

公开(公告)号：US09502530B2

公开(公告)日：2016-11-22

申请号：US14935441

申请日：2015-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chung-Fu Chang ,  Chia-Jong Liu ,  Yen-Liang Wu ,  Pei-Yu Chou ,  Home-Been Cheng

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/225 ,  H01L21/311 ,  H01L29/10 ,  H01L29/417 ,  H01L29/165

CPC classification number: H01L29/66553 ,  H01L21/2253 ,  H01L21/31133 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.

公开(公告)号：US20160315171A1

公开(公告)日：2016-10-27

申请号：US14727853

申请日：2015-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Jun-Jie Wang ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Chih-Sen Huang ,  Ching-Wen Hung ,  Hung-Chan Lin ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653

Abstract: A method for manufacturing a semiconductor device having a metal gate includes forming a filling layer and a high-K gate dielectric layer in the first recess between a pair of spacers, wherein the high-K gate dielectric layer and the filling layer are stacked in the first recess sequentially, and an exposed top surface of the high-K gate dielectric layer and a top surface of the filling layer are lower than a top surface of each spacer; and removing a part of each spacer and widening the first recess on the top surface of the filling layer to form a second recess, wherein a width of the second recess is larger than a width of the first recess.

Abstract translation: 一种具有金属栅极的半导体器件的制造方法包括在一对间隔物之间​​的第一凹部中形成填充层和高K栅极电介质层，其中高K栅极介电层和填充层堆叠在 第一凹部，高K栅极电介质层的露出顶表面和填充层的顶表面比每个间隔物的顶表面低; 并且移除每个间隔物的一部分并加宽填充层的顶表面上的第一凹部以形成第二凹部，其中第二凹部的宽度大于第一凹部的宽度。

公开(公告)号：US20160300942A1

公开(公告)日：2016-10-13

申请号：US14703904

申请日：2015-05-05

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: H01L29/78 ,  H01L21/324 ,  H01L21/02 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure thereon; forming a spacer adjacent to the first fin-shaped structure; using the spacer as mask to remove part of the substrate for forming a second fin-shaped structure, in which the second fin-shaped structure comprises a top portion and a bottom portion; and forming a doped portion in the bottom portion of the second fin-shaped structure.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有第一鳍状结构的基底; 形成邻近所述第一鳍状结构的间隔件; 使用间隔件作为掩模来去除用于形成第二鳍状结构的基板的一部分，其中第二鳍状结构包括顶部和底部; 以及在所述第二鳍状结构的底部中形成掺杂部分。

公开(公告)号：US09397190B2

公开(公告)日：2016-07-19

申请号：US14341838

申请日：2014-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Liang Wu ,  Chung-Fu Chang ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Man-Ling Lu ,  Chia-Jong Liu ,  Wen-Jiun Shen ,  Yi-Wei Chen

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/6656 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.

Abstract translation: 半导体结构的制造方法包括以下步骤。 首先，在基板上设置栅极结构，在基板和栅极结构上形成第一材料层。 接下来，在栅极结构的两侧将硼掺杂剂注入到衬底中以形成第一掺杂区，并且在栅极结构的两侧将P型导电掺杂剂注入到衬底中，以形成第二掺杂区 地区。 如下，在第一材料层上形成第二材料层。 最后，栅极结构的两侧的第二材料层，第一材料层和衬底被顺序地蚀刻，并且在栅极结构的两侧在衬底中形成凹部，其中凹部位于 第一掺杂区域。

公开(公告)号：US09281209B1

公开(公告)日：2016-03-08

申请号：US14507840

申请日：2014-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Ssu-I Fu ,  Shih-Hung Tsai ,  Yu-Hsiang Hung ,  Jyh-Shyang Jenq

IPC: G03F7/26 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/3081

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a material layer on the substrate; forming a patterned first hard mask on the material layer; forming a patterned second hard mask on the material; utilizing the patterned first hard mask and the patterned second hard mask to remove part of the material layer for forming sacrificial mandrels; forming sidewall spacers adjacent to the sacrificial mandrels; removing the sacrificial mandrels; and using the sidewall spacers to remove part of the substrate.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供衬底; 在所述基板上形成材料层; 在所述材料层上形成图案化的第一硬掩模; 在材料上形成图案化的第二硬掩模; 利用图案化的第一硬掩模和图案化的第二硬掩模去除用于形成牺牲心轴的材料层的一部分; 形成与牺牲心轴相邻的侧壁间隔物; 去除牺牲心轴; 以及使用所述侧壁间隔件来移除所述基板的一部分。