公开(公告)号：US5369049A

公开(公告)日：1994-11-29

申请号：US169873

申请日：1993-12-17

申请人： Joyce E. Acocella ,  Louis L. Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

发明人： Joyce E. Acocella ,  Louis L. Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

IPC分类号： H01L27/108 ,  H01L27/00 ,  H01L21/70

CPC分类号： H01L27/10829

摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.

摘要翻译： 一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器， 包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。 用于形成LDD源和漏极的相同侧壁形成用于将带与栅堆叠的未对准部分绝缘的表面带的自对准孔。

公开(公告)号：US4366613A

公开(公告)日：1983-01-04

申请号：US217497

申请日：1980-12-17

申请人： Seiki Ogura ,  Paul J. Tsang

发明人： Seiki Ogura ,  Paul J. Tsang

IPC分类号： H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78 ,  H01L21/26

CPC分类号： H01L27/10873 ,  H01L29/0847 ,  H01L29/78

摘要： A method of manufacturing LDD MOS FET RAM capable of delineating short (less than 1 micrometer) lightly doped drain regions. An N.sup.- implant is effected between gate electrodes and field oxide insulators, before the N.sup.+ implant. An insulator layer is then deposited also prior to N.sup.+ ion implantation. Reactive ion etching of the layer leaves narrow dimensioned insulator regions adjacent the gate electrode which serves to protect portions of the N.sup.- impurity region during the subsequent N.sup.+ implant. These protected regions are the lightly doped source/drain regions.

摘要翻译： 一种制造能够描绘短（小于1微米）轻掺杂漏极区的LDD MOS FET RAM的方法。 在N +植入之前，在栅电极和场氧化物绝缘体之间进行N-注入。 然后在N +离子注入之前也沉积绝缘体层。 层的反应离子蚀刻离开邻近栅极的窄尺寸绝缘体区域，其用于在随后的N +植入期间保护N杂质区域的部分。 这些受保护区域是轻掺杂的源极/漏极区域。

公开(公告)号：US07170132B2

公开(公告)日：2007-01-30

申请号：US11059081

申请日：2005-02-16

申请人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

公开(公告)号：US20060198200A1

公开(公告)日：2006-09-07

申请号：US11409333

申请日：2006-04-21

申请人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

发明人： Seiki Ogura ,  Kimihiro Satoh ,  Tomoya Saito

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/42364 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention proposes am improved twin MONOS memory device and its fabrication. The ONO layer is self-aligned to the control gate horizontally. The vertical insulator between the control gate and the word gate does not include a nitride layer. This prevents the problem of electron trapping. The device can be fabricated to pull the electrons out through either the top or the bottom oxide layer of the ONO insulator. The device also incorporates a raised memory bit diffusion between the control gates to reduce bit resistance. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention.

公开(公告)号：US06838344B2

公开(公告)日：2005-01-04

申请号：US10853453

申请日：2004-05-25

申请人： Kimihiro Satoh ,  Tomoya Saito ,  Seiki Ogura

发明人： Kimihiro Satoh ,  Tomoya Saito ,  Seiki Ogura

IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： The invention proposes to simplify fabrication of the twin MONOS memory array. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention by adding only three additional mask levels. Conventional floating gate devices need ten or more extra masks. In the present invention, the unique twin MONOS process steps can be inserted into the standard CMOS process flow without any parameter modifications. The present invention also achieves increased endurance by means of reducing the widths of the sidewall control gate and underlying nitride storage region.

摘要翻译： 本发明提出简化双MONOS存储器阵列的制造。 通过仅添加三个附加掩模级别，本发明的双MONOS存储器阵列可以嵌入到标准CMOS电路中。 常规浮动栅极器件需要十个或更多个额外的掩模。 在本发明中，独特的双MONOS工艺步骤可以插入到标准CMOS工艺流程中，无需任何参数修改。 本发明还通过减小侧壁控制栅极和下面的氮化物存储区域的宽度来实现增加的耐久性。

公开(公告)号：US06784040B2

公开(公告)日：2004-08-31

申请号：US10382508

申请日：2003-03-07

申请人： Masataka Kusumi ,  Fumihiko Noro ,  Hiromasa Fujimoto ,  Akihiro Kamada ,  Shinji Odanaka ,  Seiki Ogura

发明人： Masataka Kusumi ,  Fumihiko Noro ,  Hiromasa Fujimoto ,  Akihiro Kamada ,  Shinji Odanaka ,  Seiki Ogura

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

摘要翻译： 非易失性半导体存储器件具有沉积在控制栅电极的每个侧表面上的保护绝缘膜，以在形成浮栅电极期间保护控制栅电极，浮置栅极与其中一个侧表面相对 控制栅电极，其间插入有保护绝缘膜，以便电容耦合到控制栅电极，形成在浮置栅电极和半导体衬底之间的隧道绝缘膜，形成在半导体衬底的包含 并且形成在半导体衬底的与漏极区相对的控制栅电极相对的区域中的源极区。

公开(公告)号：US06686622B2

公开(公告)日：2004-02-03

申请号：US10077979

申请日：2002-02-20

申请人： Fumihiko Noro ,  Seiki Ogura

发明人： Fumihiko Noro ,  Seiki Ogura

IPC分类号： H01L2976

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： A semiconductor memory device includes a control gate electrode formed on a first main surface of a semiconductor substrate through a first insulating film, and a floating gate electrode covering a stepped region which connects the first main surface of the semiconductor substrate and a second main surface positioned at a lower level than the first main surface through a second insulating film and having a side surface capacitively coupled with one side surface of the control gate electrode through a third insulating film. The stepped region has a first stepped portion connected with the first main surface and a second stepped portion connecting the first stepped portion and the second main surface.

摘要翻译： 半导体存储器件包括通过第一绝缘膜形成在半导体衬底的第一主表面上的控制栅极电极和覆盖连接半导体衬底的第一主表面的阶梯区域的浮栅电极和位于 通过第二绝缘膜在比第一主表面更低的水平处，并且具有通过第三绝缘膜与控制栅电极的一个侧表面电容耦合的侧表面。 台阶区域具有与第一主表面连接的第一阶梯部分和连接第一阶梯部分和第二主表面的第二阶梯部分。

公开(公告)号：US6147379A

公开(公告)日：2000-11-14

申请号：US58803

申请日：1998-04-13

申请人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura ,  Kaori Akamatsu

发明人： Atsushi Hori ,  Junichi Kato ,  Shinji Odanaka ,  Seiki Ogura ,  Kaori Akamatsu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/7885

摘要： The nonvolatile semiconductor memory device of the invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first and second surface regions; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate capacitively coupled to the floating gate via a second insulating film. The first surface region is an upper surface of an epitaxially grown layer formed on the second surface region. The drain region includes: a low-concentration impurity layer formed in the second surface region and having one end extending toward the step side region; and a high-concentration impurity layer connected to the low-concentration impurity layer and formed in a region distant from the channel region. An impurity concentration of the low-concentration impurity layer is lower than that of the high-concentration impurity layer. The floating gate covers the step side region and at least a part of the low-concentration impurity layer via the first insulating film.

摘要翻译： 本发明的非易失性半导体存储器件包括：半导体衬底，具有包括第一电平的第一表面区域，低于第一电平的第二电平的第二表面区域和连接第一和第二电极的台阶侧区域的表面 表面区域 形成在所述半导体衬底的所述第一表面区域中的沟道区; 源极区域和漏极区域，其形成在半导体衬底的表面中，以便在其间插入沟道区域; 形成在所述半导体衬底的表面上的第一绝缘膜; 形成在第一绝缘膜上的浮栅; 以及经由第二绝缘膜电容耦合到浮置栅极的控制栅极。 第一表面区域是形成在第二表面区域上的外延生长层的上表面。 漏极区域包括：形成在第二表面区域中并且具有朝向台阶侧区域延伸的一端的低浓度杂质层; 以及连接到低浓度杂质层并形成在远离沟道区的区域中的高浓度杂质层。 低浓度杂质层的杂质浓度低于高浓度杂质层的杂质浓度。 浮置栅极经由第一绝缘膜覆盖台阶侧区域和至少一部分低浓度杂质层。

公开(公告)号：US6144081A

公开(公告)日：2000-11-07

申请号：US540961

申请日：1995-10-11

申请人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Lyndon Ronald Logan ,  Jack Allan Mandelman ,  Seiki Ogura

发明人： Louis Lu-Chen Hsu ,  Chang-Ming Hsieh ,  Lyndon Ronald Logan ,  Jack Allan Mandelman ,  Seiki Ogura

IPC分类号： G03F1/08 ,  H01L21/027 ,  H01L21/28 ,  H01L21/336 ,  H01L21/76 ,  H01L29/423 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/66575 ,  H01L21/28123 ,  H01L29/4238 ,  H01L29/7831

摘要： A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.

摘要翻译： 通过在第一和第二浅沟槽边缘处具有第一和第二浅沟槽之间的沟道宽度的浅沟槽隔离来隔离减轻沿着FET器件边缘感应的漏电流的场效应晶体管（FET）器件。 栅极延伸穿过第一和第二浅沟槽之间的沟道宽度。 栅极在浅沟槽边缘处具有第一长度，并且具有小于浅沟槽边缘之间的第一长度的第二长度。 第一长度和第二长度相关联，使得浅沟槽边缘处的阈值电压Vt基本上等于浅沟槽边缘之间的Vt。 FET器件的栅极结构使用独特的相移掩模产生，其允许制造具有非常小的沟道长度的亚微米FET器件。

公开(公告)号：US6074914A

公开(公告)日：2000-06-13

申请号：US182777

申请日：1998-10-30

申请人： Seiki Ogura

发明人： Seiki Ogura

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/11517 ,  H01L27/11536 ,  H01L27/11541 ,  H01L29/66825

摘要： A fabrication method for an electrically programmable read only memory device, which consists of a control/word gate and a floating gate on the side wall of the control gate. The unique material selection and blocking mask sequences allow simple and safe fabrication within the delicate scaled CMOS process environment, of a side wall floating gate with an ultra short channel under the floating gate, which involves double side wall spacer formation i.e., a disposable side wall spacer and the final polysilicon spacer gate.

摘要翻译： 一种用于电可编程只读存储器件的制造方法，其由控制/字门和控制栅极侧壁上的浮栅组成。 独特的材料选择和阻挡掩模序列允许在精细缩放的CMOS工艺环境内简单和安全地制造具有在浮动栅极下方的超短通道的侧壁浮动栅极，其涉及双侧壁间隔物形成，即一次性侧壁 间隔物和最终的多晶硅间隔栅极。