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    Semiconductor device and method for fabricating the same
    1.
    发明授权
    Semiconductor device and method for fabricating the same 失效

    公开(公告)号：US06337500B1

    公开(公告)日：2002-01-08

    申请号：US09099195

    申请日：1998-06-18

    Applicant: Hiroaki Nakaoka ,  Hiromasa Fujimoto ,  Atsushi Hori ,  Takashi Uehara ,  Takehiro Hirai

    Inventor： Hiroaki Nakaoka ,  Hiromasa Fujimoto ,  Atsushi Hori ,  Takashi Uehara ,  Takehiro Hirai

    IPC: H01L2701

    CPC classification number: H01L29/78696 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621 ,  Y10S438/91

    Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions. Thus, it is possible to provide an SOI transistor causing no decrease in the source/drain breakdown voltage resulting from substrate floating effects and causing little OFF leakage current because of the activation of the parasitic transistor.

    Method for fabricating nonvolatile semiconductor memory device
    2.
    发明授权
    Method for fabricating nonvolatile semiconductor memory device 失效
    制造非易失性半导体存储器件的方法

    公开(公告)号：US6051465A

    公开(公告)日：2000-04-18

    申请号：US126272

    申请日：1998-07-30

    Applicant: Junichi Kato ,  Atsushi Hori

    Inventor： Junichi Kato ,  Atsushi Hori

    IPC: H01L21/336 ,  H01L21/8247

    CPC classification number: H01L29/66825

    Abstract: A method for fabricating a nonvolatile semiconductor memory device according to the present invention includes the steps of: forming a first mask to define a channel of a memory cell in a semiconductor substrate; doping an impurity into the semiconductor substrate by using the first mask, thereby forming a first doped region in the semiconductor substrate; forming a second mask so as to overlap at least one of a first region of the semiconductor substrate where a source is to be formed and a second region of the semiconductor substrate where a drain is to be formed and at least part of the first mask; etching the semiconductor substrate by using the first and second masks, thereby forming a recessed portion in a region of the semiconductor substrate that is not covered with the first and second masks; forming a second doped region in the recessed portion of the semiconductor substrate; and removing the first and second masks, and forming a gate structure including a first insulating film, a floating gate electrode, a second insulating film and a control gate electrode at least over a side surface of the recessed portion and the channel defined by the first mask.

    Abstract translation: 根据本发明的制造非易失性半导体存储器件的方法包括以下步骤：形成第一掩模以限定半导体衬底中的存储单元的沟道; 通过使用第一掩模将杂质掺杂到半导体衬底中，从而在半导体衬底中形成第一掺杂区; 形成第二掩模，以便与要形成源极的半导体衬底的第一区域和要形成漏极的半导体衬底的第二区域和第一掩模的至少一部分中的至少一个重叠; 通过使用第一和第二掩模蚀刻半导体衬底，从而在未被第一和第二掩模覆盖的半导体衬底的区域中形成凹陷部分; 在所述半导体衬底的凹陷部分中形成第二掺杂区域; 以及去除第一和第二掩模，并且至少在凹部的侧表面上形成包括第一绝缘膜，浮栅电极，第二绝缘膜和控制栅电极的栅结构，以及由第一绝缘膜， 面具。

    Semiconductor device for protecting an internal circuit from electrostatic damage
    3.
    发明授权
    Semiconductor device for protecting an internal circuit from electrostatic damage 失效
    用于保护内部电路免受静电损坏的半导体器件

    公开(公告)号：US5514893A

    公开(公告)日：1996-05-07

    申请号：US207426

    申请日：1994-03-08

    Applicant: Isao Miyanaga ,  Kazumi Kurimoto ,  Atsushi Hori ,  Shinji Odanaka

    Inventor： Isao Miyanaga ,  Kazumi Kurimoto ,  Atsushi Hori ,  Shinji Odanaka

    IPC: H01L27/02 ,  H03K19/003 ,  H01L23/62 ,  H02H3/20 ,  H02H9/00 ,  H03K17/60

    CPC classification number: H01L27/0259 ,  H01L27/0266 ,  H03K19/00315

    Abstract: A semiconductor device includes an input/output terminal, an internal circuit connected to the input/output terminal, a first terminal for providing a first electrical potential, and a second terminal for providing a second electrical potential which is lower than the first electrical potential, the device further including: a first n-channel MOS transistor having a drain connected to the input/output terminal, a source connected to the second terminal, and a gate to be electrically connected to the first terminal; and a first switching element for switching between an electrically conductive state and a non-conductive state between the drain and the gate of the first n-channel MOS transistor, the switching element forming the electrically conductive state between the drain and the gate of the first n-channel MOS transistor when 1) a surge voltage lower than the first electrical potential is applied to the input/output terminal, and 2) an electrical potential difference between the drain and the gate of the first n-channel MOS transistor exceeds a predetermined voltage lower than a breakdown voltage of the gate of the first n-channel MOS transistor. The formation of the electrically conductive state prevents the gate oxide of the first n-channel MOS transistor from being damaged.

    Abstract translation: 半导体器件包括输入/​​输出端子，连接到输入/输出端子的内部电路，用于提供第一电位的第一端子和用于提供低于第一电位的第二电位的第二端子， 该器件还包括：第一n沟道MOS晶体管，具有连接到输入/输出端子的漏极，连接到第二端子的源极和与第一端子电连接的栅极; 以及用于在第一n沟道MOS晶体管的漏极和栅极之间切换导电状态和非导通状态的第一开关元件，所述开关元件在第一N沟道MOS晶体管的漏极和栅极之间形成导电状态 n沟道MOS晶体管，当1）低于第一电位的浪涌电压被施加到输入/输出端时，以及2）第一n沟道MOS晶体管的漏极和栅极之间的电位差超过预定的 电压低于第一n沟道MOS晶体管的栅极的击穿电压。 导电状态的形成防止了第一n沟道MOS晶体管的栅极氧化物被损坏。

    Fabrication method for semiconductor devices
    4.
    发明授权
    Fabrication method for semiconductor devices 失效
    半导体器件制造方法

    公开(公告)号：US5296388A

    公开(公告)日：1994-03-22

    申请号：US729490

    申请日：1991-07-12

    Applicant: Shuichi Kameyama ,  Atsushi Hori ,  Hiroshi Shimomura ,  Mizuki Segawa

    Inventor： Shuichi Kameyama ,  Atsushi Hori ,  Hiroshi Shimomura ,  Mizuki Segawa

    IPC: H01L21/20 ,  H01L21/265 ,  H01L21/285 ,  H01L21/331

    CPC classification number: H01L29/66272 ,  H01L21/2022 ,  H01L21/2652 ,  H01L21/28525 ,  Y10S148/011 ,  Y10S148/124 ,  Y10S438/969

    Abstract: A fabrication method for semiconductor devices connecting a multi-crystal semiconductor thin film and a semiconductor region including a high density of an impurity formed in a single crystal semiconductor substrate. After forming a N-type semiconductor region as the emitter by ion implanting, for instance, as into a P-type semiconductor region as the base, a polysilicon thin film 114 is deposited so as to be implanted with As ions and then heat treated. In this case, an amorphous portion of the N-type semiconductor region and an amorphous silicon thin film in contact therewith are transformed by solid phase epitaxial growth so as to form a single crystal semiconductor region, a single-crystalline silicon thin film, and a polysilicon thin film, thus forming a bipolar element having an emitter.

    Abstract translation: 连接多晶半导体薄膜和包含在单晶半导体衬底中形成的高浓度杂质的半导体区域的半导体器件的制造方法。 在通过离子注入形成作为发射极的N型半导体区域之后，例如作为基底的P型半导体区域，沉积多晶硅薄膜114，以便注入As离子，然后进行热处理。 在这种情况下，通过固相外延生长来转变N型半导体区域的非晶部分和与其接触的非晶硅薄膜，从而形成单晶半导体区域，单晶硅薄膜和 多晶硅薄膜，从而形成具有发射极的双极元件。

    Method for manufacturing bipolar semiconductor device
    5.
    发明授权
    Method for manufacturing bipolar semiconductor device 失效
    制造双极型半导体器件的方法

    公开(公告)号：US5254485A

    公开(公告)日：1993-10-19

    申请号：US760987

    申请日：1991-09-17

    Applicant: Mizuki Segawa ,  Shuichi Kameyama ,  Hiroshi Shimomura ,  Atsushi Hori

    Inventor： Mizuki Segawa ,  Shuichi Kameyama ,  Hiroshi Shimomura ,  Atsushi Hori

    IPC: H01L21/331 ,  H01L21/265 ,  H01L29/70

    CPC classification number: H01L29/66272 ,  Y10S148/01

    Abstract: There is disclosed a method for manufacturing a bipolar semiconductor device in which emitter region and active base region are formed by implanting impurities of first and second conduction types in a first semiconductor region of the first conduction type to be a collector through a non-single crystalline semiconductor thin film, a second semiconductor thin film is formed on the first semiconductor thin film, and an impurity of the first conduction type is introduced in the second semiconductor thin film after patterning the first and second semiconductor thin film so as to form an emitter electrode.

    Abstract translation: 公开了一种制造双极型半导体器件的方法，其中通过将第一和第二导电类型的杂质注入第一导电类型的第一半导体区域中作为集电极的非单晶结构形成发射极区域和有源基极区域 在第一半导体薄膜上形成第二半导体薄膜，在对第一和第二半导体薄膜进行图案化之后，将第一导电类型的杂质引入到第二半导体薄膜中，以形成发射极 。

    Image processing device and image processing program
    9.
    发明授权
    Image processing device and image processing program 有权
    图像处理装置和图像处理程序

    公开(公告)号：US08358442B2

    公开(公告)日：2013-01-22

    申请号：US12446348

    申请日：2006-11-16

    Applicant: Toshiyuki Takahashi ,  Atsushi Hori ,  Yuka Fujita ,  Koichi Hiramatsu ,  Takeo Kawaura

    Inventor： Toshiyuki Takahashi ,  Atsushi Hori ,  Yuka Fujita ,  Koichi Hiramatsu ,  Takeo Kawaura

    IPC: H04N1/40 ,  G06F3/12

    CPC classification number: G06T5/30 ,  G06T11/203

    Abstract: An image processing device includes a multiplier 1 for multiplying a pixel signal P(x) by a weighting factor α0 (0≦α0≦1), a delay element 2 for delaying the pixel signal P(x) which has not been multiplied yet by the weighting factor α0 by the multiplier 1 by one pixel, and a multiplier 3 for multiplying the pixel signal P(x−1) delayed by the delay element 2 by a weighting factor α1 (0≦α1≦1), the total sum of the weighting factors α0 and α1 being larger than 1 and smaller than an upper limit αmax. An adder 4 adds the multiplication result α0·P(x) of the multiplier 1 and the multiplication result α1·P(x−1) of the multiplier 3, and a limiter 5 limits the addition result P′(x) of the adder 4 in such a way that P′(x) falls within a maximum density value Pmax.

    Abstract translation: 图像处理装置包括：乘法器1，用于将像素信号P（x）乘以加权因子α0（0＆amp; nlE;α0＆nlE; 1）;延迟元件2，用于将未被乘以的像素信号P（x） 乘法器1的加权因子α0乘以一个像素，乘法器3将由延迟元件2延迟的像素信号P（x-1）乘以加权因子α1（0＆nlE;α1＆nlE; 1），总和 加权系数α0，α1大于1，小于上限αmax。 加法器4将乘法器1的相乘结果α0·P（x）和乘法器3的相乘结果α1·P（x-1）相加，限制器5限制加法器的相加结果P'（x） 4，使得P'（x）落在最大密度值Pmax内。

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