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    Fabrication methods for high performance lateral bipolar transistors
    2.
    发明授权
    Fabrication methods for high performance lateral bipolar transistors 失效
    高性能横向双极晶体管的制造方法

    公开(公告)号：US4546536A

    公开(公告)日：1985-10-15

    申请号：US520365

    申请日：1983-08-04

    申请人： Narasipur G. Anantha ,  Jacob Riseman ,  Paul J. Tsang

    发明人： Narasipur G. Anantha ,  Jacob Riseman ,  Paul J. Tsang

    IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L21/22 ,  H01L21/76 ,  H01L27/08

    CPC分类号： H01L29/6625 ,  H01L21/743 ,  H01L21/8224 ,  H01L29/735 ,  Y10S148/01

    摘要： The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ buried layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base a insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

    摘要翻译： 描述了具有其基极宽度和晶体管的发射极区域最小化的横向晶体管。 横向晶体管的元件的这种最小化给出了高性能。 通常可以是PNP晶体管的横向晶体管形成在体内具有掩埋的N +区域的单晶半导体本体。 P型发射体区域位于体内。 N型基极区域位于发射极区域的侧边周围。 P型集电极区域位于围绕基极区域周边的主体中。 作为发射极区域的发射极接触点的第一P +多晶硅层与发射极区物理和电接触，并充当其电接触。 第二个P +多晶硅层位于主体的表面上，以与收集器区域物理和电接触。 在第二多晶硅层的边缘上的垂直绝缘体层将两个多晶硅层彼此隔离。 其表面的N基区位于垂直绝缘体层的宽度的下方。 从主体的表面向掩埋的N +区域延伸的N +通孔区域用作通过N +掩埋层到基极区域的电接触。 垂直绝缘体的宽度具有等于横向PNP晶体管的期望基极宽度以及横向PNP的集电极和发射极结的横向扩散的宽度。 优选的结构是使发射体形成在通道或槽的周边周围，该通道或槽在其底部具有诸如二氧化硅的绝缘层。 寄生晶体管几乎完全被这种掩埋氧化物隔离所消除。

    Methods for making high performance lateral bipolar transistors
    3.
    发明授权
    Methods for making high performance lateral bipolar transistors 失效
    制造高性能横向双极晶体管的方法

    公开(公告)号：US4492008A

    公开(公告)日：1985-01-08

    申请号：US520366

    申请日：1983-08-04

    申请人： Narasipur G. Anantha ,  Tak H. Ning ,  Paul J. Tsang

    发明人： Narasipur G. Anantha ,  Tak H. Ning ,  Paul J. Tsang

    IPC分类号： H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L27/08 ,  H01L21/76

    CPC分类号： H01L29/6625 ,  H01L21/743 ,  H01L21/8224 ,  H01L27/0821 ,  H01L29/735

    摘要： A high performance lateral transistor may be fabricated by first providing a monocrystalline semiconductor body having a principal surface and where the desired transistor is a PNP transistor, a buried N+ region with an N+ reach-through connecting the buried region to said principal surface. The collector region of the transistor is formed into the surface by blanket diffusing P type impurities into the desired region. An insulating layer is formed upon the top surface of the semiconductor body. An opening is made in the insulating layer where the groove or channel-emitter contact is desired. An etching of a substantially vertical walled groove into the monocrystalline semiconductor body using the patterned insulating layer as the etching mask. An N base diffusion is carried out to produce as N region around the periphery of the opening in the body. Oxygen is then ion implanted into the bottom of the groove to form a silicon dioxide region at the bottom of the groove. The P+ polycrystalline silicon layer is then formed on the surface which will in turn fill the groove with this material. The heating of the structure forms the P+ emitter region around the side edges of the P+ polycrystalline silicon filled groove. The P+ polycrystalline layer is the emitter contact, the N+ reach-through connected through the buried N+ region is the base contact and the collector contact is made to the P-type collector region.

    摘要翻译： 可以通过首先提供具有主表面的单晶半导体主体并且其中期望的晶体管是PNP晶体管，具有将掩埋区域连接到所述主表面的N +到达通孔的掩埋N +区域来制造高性能横向晶体管。 晶体管的集电极区域通过将P型杂质铺展成期望的区域而形成为表面。 绝缘层形成在半导体本体的顶表面上。 在需要沟槽或沟道 - 发射极接触的绝缘层中形成开口。 使用图案化绝缘层作为蚀刻掩模，将基本垂直的壁槽蚀刻到单晶半导体本体中。 进行N基扩散以在体内的开口的周边周围产生N区。 然后将氧离子注入凹槽的底部，以在凹槽的底部形成二氧化硅区域。 然后在表面上形成P +多晶硅层，该表面依次用该材料填充凹槽。 结构的加热在P +多晶硅填充槽的侧边缘周围形成P +发射极区域。 P +多晶层是发射极接触，通过埋入N +区连接的N +到达通孔是基极接触，并且集电极接触到P型集电极区域。

    Formation of bit lines for ram device
    5.
    发明授权
    Formation of bit lines for ram device 失效
    形成柱塞装置的位线

    公开(公告)号：US4403394A

    公开(公告)日：1983-09-13

    申请号：US217371

    申请日：1980-12-17

    申请人： Joseph F. Shepard ,  Paul J. Tsang

    发明人： Joseph F. Shepard ,  Paul J. Tsang

    IPC分类号： H01L27/10 ,  H01L21/28 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/532 ,  H01L27/108 ,  H01L29/78 ,  H01L21/22

    CPC分类号： H01L21/76889 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S438/98

    摘要： A conductor bit line for a dynamic random access memory (RAM) structure is formed of a material selected from the group consisting of polycrystalline silicon and a metal silicide, polycrystalline silicon and a conductive metal, and polycrystalline silicon, a metal silicide, and a conductive metal with the polycrystalline silicon contacting at least a portion of the drain region of the field effect transistor of each of a plurality of cells of the RAM structure via a self-aligned contact. When the selected material is polycrystalline silicon and a metal silicide, the conductor bit line is continuous. When the selected material is polycrystalline silicon and a conductive metal or polycrystalline silicon, a metal silicide, and a conductive metal, the polycrystalline silicon contacts with each of the drain regions while the conductive metal connects the polycrystalline silicon overlying adjacent drain regions when the selected material is polycrystalline silicon and a conductive metal and connects the metal silicide on the polycrystalline silicon overlying adjacent drain regions when the selected material is polycrystalline silicon, a metal silicide, and a conductive metal.

    摘要翻译： 用于动态随机存取存储器（RAM）结构的导体位线由选自多晶硅和金属硅化物，多晶硅和导电金属的组中的材料形成，多晶硅，金属硅化物和导电 金属与多晶硅经由自对准接触接触RAM结构的多个单元中的每一个的场效应晶体管的漏极区域的至少一部分。 当所选择的材料是多晶硅和金属硅化物时，导体位线是连续的。 当所选择的材料是多晶硅和导电金属或多晶硅，金属硅化物和导电金属时，多晶硅与每个漏极区接触，而当所选材料的导电金属连接覆盖相邻漏极区的多晶硅时 是多晶硅和导电金属，并且当所选择的材料是多晶硅，金属硅化物和导电金属时，将覆盖在相邻漏极区域上的多晶硅上的金属硅化物连接。

    Inverse T-gate FET transistor with lightly doped source and drain region
    6.
    发明授权
    Inverse T-gate FET transistor with lightly doped source and drain region 失效
    具有轻掺杂源极和漏极区域的反向T栅极FET晶体管

    公开(公告)号：US5241203A

    公开(公告)日：1993-08-31

    申请号：US824228

    申请日：1992-01-22

    申请人： Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard ,  Paul J. Tsang

    发明人： Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard ,  Paul J. Tsang

    IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/78

    CPC分类号： H01L29/66606 ,  H01L29/42376 ,  H01L29/7836 ,  H01L2924/0002

    摘要： A lightly doped drain, field effect transistor with an inverted "T"-gate structure has a gate electrode disposed on a polysilicon pad in a stack opening. The inner edge of a lightly-doped source and drain region is aligned with the gate electrode and its outer edge is aligned with an edge of the polysilicon pad. The inner edge of a heavily-doped source and drain region is aligned with the edge of the edge of the polysilicon pad and its outer edge is aligned with the wall surface that forms the opening. The inner edge of a source and drain contact region is aligned with the wall and extends under the stack.

    摘要翻译： 具有反向“T” - 门结构的轻掺杂漏极场效应晶体管具有设置在堆叠开口中的多晶硅焊盘上的栅电极。 轻掺杂源极和漏极区域的内边缘与栅电极对准，并且其外边缘与多晶硅焊盘的边缘对准。 重掺杂源极和漏极区域的内边缘与多晶硅焊盘的边缘的边缘对准，并且其外边缘与形成开口的壁表面对准。 源极和漏极接触区域的内边缘与壁对准并在堆叠下方延伸。

    Process of making BiCMOS devices having closely spaced device regions
    7.
    发明授权
    Process of making BiCMOS devices having closely spaced device regions 失效
    制造具有紧密间隔的器件区域的BiCMOS器件的工艺

    公开(公告)号：US5015594A

    公开(公告)日：1991-05-14

    申请号：US261952

    申请日：1988-10-24

    申请人： Shao-Fu S. Chu ,  San-Mei Ku ,  Russell C. Lange ,  Joseph F. Shephard ,  Paul J. Tsang ,  Wen-Yuan Wang

    发明人： Shao-Fu S. Chu ,  San-Mei Ku ,  Russell C. Lange ,  Joseph F. Shephard ,  Paul J. Tsang ,  Wen-Yuan Wang

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

    CPC分类号： H01L21/76897 ,  H01L21/8249 ,  Y10S148/009

    摘要： A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall.In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact.The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

    Method for forming recessed regions of thermally oxidized silicon and structures thereof utilizing anisotropic etching
    9.
    发明授权
    Method for forming recessed regions of thermally oxidized silicon and structures thereof utilizing anisotropic etching 失效
    利用各向异性蚀刻形成热氧化硅的凹陷区域及其结构的方法

    公开(公告)号：US3998674A

    公开(公告)日：1976-12-21

    申请号：US634571

    申请日：1975-11-24

    申请人： Donald P. Cameron ,  Paul J. Tsang

    发明人： Donald P. Cameron ,  Paul J. Tsang

    IPC分类号： H01L21/76 ,  H01L21/306 ,  H01L21/32 ,  H01L21/762 ,  H01L21/20

    CPC分类号： H01L21/76202 ,  H01L21/30608 ,  H01L21/32 ,  Y10S438/973

    摘要： An improved method for forming a recessed thermal SiO.sub.2 isolation region in a monocrystalline silicon semiconductor body having a major surface lying in a (100) plane as defined by the Miller indices by forming an etch resistant and oxidation resistant masking layer on the major surface of the body, forming at least one rectilinear annular opening in the masking layer, the opening being oriented with the sides parallel to the [100] directions on the major surface, removing a portion of the exposed body by anisotropic chemical etching, and oxidizing the resultant exposed portions of the body until the surface of the resultant SiO.sub.2 and major surface are substantially coplanar.A semiconductor device including a silicon substrate of a first conductivity, the major surface being in the (100) plane, an epitaxial silicon layer on the substrate, a lateral PN junction in the substrate, at least one annular rectangular shaped recessed SiO.sub.2 region in the epitaxial layer extending inwardly to the PN junction, the annular region being oriented with the sides parallel to the [100] direction on the major surface.

    摘要翻译： 一种用于在单晶硅半导体器件中形成凹陷的热二氧化硅隔离区域的改进方法，其具有位于（100）平面中的主要表面，如由米勒指数所限定的，其在主表面上形成耐蚀刻和抗氧化掩蔽层 在掩模层中形成至少一个直线环形开口，该开口在主表面上平行于[100]方向取向，通过各向异性化学蚀刻去除一部分暴露体，并将所得暴露 直到所得SiO 2和主表面的表面基本上共面为止。