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公开(公告)号：US4392149A
公开(公告)日：1983-07-05
申请号：US273705
申请日：1981-06-15
IPC分类号： H01L21/033 , H01L21/331 , H01L21/8222 , H01L29/08 , H01L29/732 , H01L27/12
CPC分类号： H01L29/66272 , H01L21/0332 , H01L21/0337 , H01L21/8222 , H01L29/0804 , H01L29/7325
摘要： Disclosed is a self-aligned process for providing an improved bipolar transistor structure.The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.
摘要翻译： 公开了一种用于提供改进的双极晶体管结构的自对准工艺。 该方法包括中间绝缘层的化学蚀刻，以在自对准发射极工艺中切割出不同绝缘材料的另一顶层，其中发射极接触与多晶硅基底接触的间隔减小到约0.2至0.3的量级 微米。 此外，在该过程中，形成发射极插塞以阻挡来自外部基极的重P +离子剂量植入物的发射极区域。
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2.发明授权Process for fabricating improved bipolar transistor utilizing selective etching 失效利用选择性蚀刻制造改进的双极晶体管的工艺
公开(公告)号：US4309812A
公开(公告)日：1982-01-12
申请号：US126610
申请日：1980-03-03
IPC分类号： H01L29/73 , H01L21/033 , H01L21/331 , H01L21/60 , H01L21/762 , H01L29/08 , H01L29/732 , H01L21/265 , H01L21/285 , H01L21/31
CPC分类号： H01L21/76897 , H01L21/0332 , H01L21/0337 , H01L21/76229 , H01L29/0804 , H01L29/66272 , H01L29/7325 , Y10S148/131 , Y10S438/951
摘要： Disclosed is a self-aligned process for providing an improved bipolar transistor structure.The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.
摘要翻译： 公开了一种用于提供改进的双极晶体管结构的自对准工艺。 该方法包括中间绝缘层的化学蚀刻，以在自对准发射极工艺中切割出不同绝缘材料的另一顶层，其中发射极接触与多晶硅基底接触的间隔减小到约0.2至0.3的量级 微米。 此外，在该过程中，形成发射极插塞以阻挡来自外部基极的重P +离子剂量植入物的发射极区域。
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公开(公告)号：US4378630A
公开(公告)日：1983-04-05
申请号：US309627
申请日：1981-10-08
IPC分类号： H01L21/331 , H01L21/762 , H01L21/8224 , H01L27/082 , H01L29/10 , H01L29/423 , H01L21/203 , H01L21/22
CPC分类号： H01L29/66272 , H01L21/76202 , H01L21/76229 , H01L21/76232 , H01L21/8224 , H01L27/0821 , H01L29/1004 , H01L29/42304
摘要： Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.
摘要翻译： 公开了具有非常高的速度和低功率要求的PNP和NPN类型的非常小的集成电路器件的制造和结构。 该结构提供了在同一半导体芯片内形成的垂直NPN和横向PNP晶体管。 横向PNP晶体管的基极宽度非常窄（约300至400纳米）。 这个窄尺寸部分通过使用明确定义的化学气相沉积（CVD）氧化物掩模而不是常规的光刻掩模来获得。 为了消除注入衬底的发射极电流，PNP晶体管的P +发射极和P +集电极由氮化硅和二氧化硅介电层界定。
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公开(公告)号：US4338138A
公开(公告)日：1982-07-06
申请号：US126611
申请日：1980-03-03
申请人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
发明人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
IPC分类号： H01L21/8222 , H01L21/033 , H01L21/285 , H01L21/331 , H01L21/762 , H01L27/06 , H01L29/73 , H01L29/732 , H01L21/263 , H01L21/203 , H01L21/22 , H01L21/31
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/28525 , H01L21/76229 , H01L21/76232 , H01L29/7325 , Y10S148/131
摘要： An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.
摘要翻译： 一种改进的双极晶体管结构，其形成在第一导电类型的硅衬底的平坦表面上的薄外延层的非常小的区域中，所述薄外延层的非常小的面积具有延伸到所述衬底的平坦表面的垂直侧壁， 所述薄外延层的区域包含按顺序列出的具有暴露平面的第二导电类型的浅深度发射极区域，所述第一导电类型的浅深度基底区域和所述第二导电类型的浅深度有源集电极区域 围绕所述发射极，基极和主动集电极区域的所述第一导电类型的细长区域，所述细长区域包含在所述薄外延层的所述小区域的所述垂直侧壁内并与之共同延伸，由此基极集电极电容由于 到基极 - 集电极结的非常小的区域。 还公开了用于制造改进的双极晶体管结构的工艺和替代工艺。
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公开(公告)号：US4303933A
公开(公告)日：1981-12-01
申请号：US98588
申请日：1979-11-29
IPC分类号： H01L21/76 , H01L21/331 , H01L21/74 , H01L21/762 , H01L29/08 , H01L29/10 , H01L29/73 , H01L29/732 , H01L27/04 , H01L29/72
CPC分类号： H01L21/743 , H01L21/76229 , H01L21/76232 , H01L29/0804 , H01L29/1004 , H01L29/7325 , Y10S148/131
摘要： A method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base.
摘要翻译： 公开的器件制造方法是自对准工艺。 形成的装置具有小的垂直和水平尺寸。 器件区域被具有几乎垂直侧壁的深氧化物沟槽围绕。 深沟槽从外延硅表面通过N +子集电极区域延伸到P衬底中。 深沟的宽度约为2〜3.0亩。 从外延硅表面延伸到N +子集电极的上部的浅氧化物沟槽分离基极和集电极触点。 隔离区域和形成晶体管的硅的表面是共面的。 如图所示。 如图1所示，制造的双极晶体管具有台面型结构。 晶体管基极尺寸仅略大于发射极。 这种小的基极面积导致集电极电容低，这是超高性能集成电路器件中非常重要的参数。 所公开的结构中与晶体管基极的接触是通过围绕发射极的厚的重硼掺杂的多晶硅层实现的，并且与活性基底进行横向接触。
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6.发明授权Process for making large area isolation trenches utilizing a two-step selective etching technique 失效利用两步选择性蚀刻技术制造大面积隔离沟槽的方法
公开(公告)号：US4211582A
公开(公告)日：1980-07-08
申请号：US52997
申请日：1979-06-28
IPC分类号： H01L21/76 , H01L21/033 , H01L21/263 , H01L21/302 , H01L21/3065 , H01L21/316 , H01L21/762 , H01L21/768 , H01L21/306
CPC分类号： H01L21/0337 , H01L21/2633 , H01L21/3065 , H01L21/76208 , H01L21/76229 , H01L21/768 , H01L21/76877 , Y10S148/05 , Y10S148/051 , Y10S148/085 , Y10S148/106 , Y10S148/111 , Y10S148/131
摘要： A method for making wide, deep recessed oxide isolation trenches in silicon semiconductor substrates. A semi-conductor substrate is selectively etched to produce a spaced succession of narrow, shallow trenches separated by narrow silicon mesas. Silicon oxide is chemical-vapor-deposited on the horizontal and vertical surfaces of the etched structure to a thickness equalling the width of a desired silicon oxide mask. The mask is used for etching multiple deep trenches in the substrate, the trenches being separated by thin walls of silicon. The thickness of the walls is uniformly equal to and determined by the thickness of the deposited silicon oxide mask.The deposited silicon oxide is reactively ion etched away from the horizontal surfaces, leaving the oxide only on the sidewalls of the shallow trenches. The silicon is deeply etched, using the remaining oxide as a mask. Boron is ion implanted and the resulting structure is thermally oxidized sufficiently to completely oxidize the silicon under the deposited oxide mask and to oxidize the silicon surfaces at the bottoms of the trenches. The remaining trench volume is filled in with chemical-vapor-deposited silicon dioxide.
摘要翻译： 一种用于在硅半导体衬底中制造宽的深凹陷氧化物隔离沟槽的方法。 选择性地蚀刻半导体衬底以产生由狭窄的硅台面分开的间隔一连串的窄的浅沟槽。 氧化硅在蚀刻结构的水平和垂直表面上化学气相沉积到等于所需氧化硅掩模宽度的厚度。 掩模用于蚀刻衬底中的多个深沟槽，沟槽被薄壁的硅分隔开。 壁的厚度均匀地等于并由沉积的氧化硅掩模的厚度确定。 沉积的氧化硅被离子蚀刻离开水平表面，仅将氧化物留在浅沟槽的侧壁上。 硅被深刻蚀刻，使用剩余的氧化物作为掩模。 硼离子注入，并且所得结构被充分热氧化以在沉积的氧化物掩模下完全氧化硅，并在沟底部氧化硅表面。 剩余的沟槽体积填充有化学气相沉积的二氧化硅。
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公开(公告)号：US5271802A
公开(公告)日：1993-12-21
申请号：US987509
申请日：1992-12-07
CPC分类号： G11B5/3106 , G11B5/6005 , Y10T29/49052
摘要： A method for making a magnetic head slider having a protective coating on the rails thereof, the protective coating containing a thin adhesion layer, a thin layer of amorphous hydrogenated carbon, and a thin masking layer. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.
摘要翻译： 一种用于制造在其轨道上具有保护涂层的磁头滑块的方法，所述保护涂层包含薄粘合层，非晶氢化碳薄层和薄掩蔽层。 在将薄膜磁头研磨成选定的尺寸之后，但是在空气轴承表面上产生轨道图案之前，保护涂层沉积在滑块的空气支承表面上。 保护涂层在轨道制造过程中保护磁头，并且在磁记录系统中使用可保护磁头免受磨损和腐蚀的损害。
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公开(公告)号：US5198090A
公开(公告)日：1993-03-30
申请号：US807766
申请日：1991-12-06
CPC分类号： C23C14/225 , C23C14/34 , H01J37/34 , H01J37/3426 , H01J37/3447
摘要： A sputtering apparatus for coating a substrate comprising a first electrode for supporting a target material and a second electrode for supporting a substrate, upon which the coating is deposited. A source of RF power is connected to impose an RF voltage across the electrodes to produce a glow discharge in the space between the electrodes, and shutter means is provided in the space between the electrodes. The shutter means has means for blocking a substantial part of the sputtered atoms from the target electrode glow discharge traveling at or near normal incidence and at least one opening shaped to permit a substantial part of the sputtered atoms from the target electrode traveling at an oblique angle to impinge upon the substrate to produce a thin film coating of the target material.
摘要翻译： 一种用于涂覆基板的溅射装置，包括用于支撑目标材料的第一电极和用于支撑基板的第二电极，在该基板上沉积涂层。 RF电源连接以在电极之间施加RF电压以在电极之间的空间中产生辉光放电，并且在电极之间的空间中设置快门装置。 快门装置具有用于阻挡大部分溅射原子从在正常入射处或接近正常入射处行进的目标电极辉光放电的至少一个开口，至少一个开口成形为允许来自目标电极的大部分溅射原子以倾斜角行进 以撞击基板以产生目标材料的薄膜涂层。
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9.发明授权
公开(公告)号：US5175658A
公开(公告)日：1992-12-29
申请号：US634834
申请日：1990-12-27
CPC分类号： G11B5/6005 , G11B5/3106
摘要： A magnetic head slider having a protective coating on the rails thereof, the protective coating comprising a thin adhesion layer, a thin layer of amorphous hydrogenated carbon, and a thin masking layer. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.
摘要翻译： 一种在其轨道上具有保护涂层的磁头滑块，保护涂层包括薄的粘合层，非晶氢化碳的薄层和薄的掩蔽层。 在将薄膜磁头研磨成选定的尺寸之后，但是在空气轴承表面上产生轨道图案之前，保护涂层沉积在滑块的空气支承表面上。 保护涂层在轨道制造过程中保护磁头，并且在磁记录系统中使用可保护磁头免受磨损和腐蚀的损害。
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公开(公告)号：UST106101I4
公开(公告)日：1985-12-03
申请号：US695657
申请日：1985-01-28
申请人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
发明人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
IPC分类号： H01L21/285 , H01L21/331 , H01L21/762 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/28525 , H01L21/76229 , H01L21/76232 , H01L29/7325
摘要： An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layer containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction.
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