公开(公告)号：US4378630A

公开(公告)日：1983-04-05

申请号：US309627

申请日：1981-10-08

申请人： Cheng T. Horng ,  Richard R. Konian ,  Robert O. Schwenker ,  Armin W. Weider

发明人： Cheng T. Horng ,  Richard R. Konian ,  Robert O. Schwenker ,  Armin W. Weider

IPC分类号： H01L21/331 ,  H01L21/762 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/10 ,  H01L29/423 ,  H01L21/203 ,  H01L21/22

CPC分类号： H01L29/66272 ,  H01L21/76202 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/8224 ,  H01L27/0821 ,  H01L29/1004 ,  H01L29/42304

摘要： Disclosed is the fabrication and structure of very small integrated circuit devices of both PNP and NPN types with very high speeds and low power requirements. The structure provides vertical NPN and lateral PNP transistors formed within the same semiconductor chip. The base width of the lateral PNP transistor is very narrow (approximately 300 to 400 nanometers). This narrow dimension is in part obtained by using a well defined chemically vapor deposited (CVD) oxide mask instead of conventional lithographic masking. To eliminate the emitter current injecting into the substrate the P+ emitter and P+ collector of the PNP transistor are bounded by a silicon nitride and silicon dioxide dielectric layer.

摘要翻译： 公开了具有非常高的速度和低功率要求的PNP和NPN类型的非常小的集成电路器件的制造和结构。 该结构提供了在同一半导体芯片内形成的垂直NPN和横向PNP晶体管。 横向PNP晶体管的基极宽度非常窄（约300至400纳米）。 这个窄尺寸部分通过使用明确定义的化学气相沉积（CVD）氧化物掩模而不是常规的光刻掩模来获得。 为了消除注入衬底的发射极电流，PNP晶体管的P +发射极和P +集电极由氮化硅和二氧化硅介电层界定。