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公开(公告)号：US4303933A
公开(公告)日：1981-12-01
申请号：US98588
申请日：1979-11-29
IPC分类号： H01L21/76 , H01L21/331 , H01L21/74 , H01L21/762 , H01L29/08 , H01L29/10 , H01L29/73 , H01L29/732 , H01L27/04 , H01L29/72
CPC分类号： H01L21/743 , H01L21/76229 , H01L21/76232 , H01L29/0804 , H01L29/1004 , H01L29/7325 , Y10S148/131
摘要： A method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3.0 .mu.m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base.
摘要翻译： 公开的器件制造方法是自对准工艺。 形成的装置具有小的垂直和水平尺寸。 器件区域被具有几乎垂直侧壁的深氧化物沟槽围绕。 深沟槽从外延硅表面通过N +子集电极区域延伸到P衬底中。 深沟的宽度约为2〜3.0亩。 从外延硅表面延伸到N +子集电极的上部的浅氧化物沟槽分离基极和集电极触点。 隔离区域和形成晶体管的硅的表面是共面的。 如图所示。 如图1所示，制造的双极晶体管具有台面型结构。 晶体管基极尺寸仅略大于发射极。 这种小的基极面积导致集电极电容低，这是超高性能集成电路器件中非常重要的参数。 所公开的结构中与晶体管基极的接触是通过围绕发射极的厚的重硼掺杂的多晶硅层实现的，并且与活性基底进行横向接触。
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公开(公告)号：US4593307A
公开(公告)日：1986-06-03
申请号：US509732
申请日：1983-06-30
申请人： Hans S. Rupprecht , Sandip Tiwari
发明人： Hans S. Rupprecht , Sandip Tiwari
IPC分类号： H01L29/43 , H01L21/28 , H01L21/285 , H01L29/45 , H01L23/48
CPC分类号： H01L21/28575 , H01L29/452 , Y10S148/084 , Y10S148/14
摘要： This invention relates generally to ohmic contacts to substrates made of III-V compounds and to a process for fabricating such contacts. More specifically, the invention is directed to a contact to gallium arsenide having a given level of n-type dopant therein, a region of the substrate doped with germanium and a layer of a germanide of a refractory metal selected from the group consisting of molybdenum, tungsten and tantalum disposed on the substrate. Still more specifically, the invention relates to an ohmic contact to gallium arsenide which includes an interface region of germanium heavily doped with arsenic disposed between the region doped with germanium and the layer of germanide. The contact is formed by evaporating germanium and a refractory metal selected from the group consisting of molybdenum, tungsten and tantalum on the surface of an n-type gallium arsenide substrate and sintering the substrate in a reducing atmosphere for a time and at a temperature sufficient to form the first-to-form germanide of the refractory metal. The resulting contact is stable, has a very low contact resistance and may be subjected to later high temperature processing steps without affecting its characteristics.
摘要翻译： 本发明一般涉及由III-V化合物制成的衬底的欧姆接触以及制造这种接触的方法。 更具体地，本发明涉及其中具有给定水平的n型掺杂剂的砷化镓的接触，掺杂有锗的衬底的区域和选自钼， 设置在基板上的钨和钽。 更具体地，本发明涉及对砷化镓的欧姆接触，其包括重掺杂砷的锗的界面区域，其设置在掺杂有锗的区域和锗化物层之间。 接触是通过在n型砷化镓衬底的表面上蒸发锗和选自钼，钨和钽的难熔金属形成的，并在还原气氛中烧结衬底一段时间并在足以 形成难熔金属的第一个到形式的锗化物。 所得到的接触是稳定的，具有非常低的接触电阻并且可以经受稍后的高温处理步骤而不影响其特性。
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3.发明授权Method of making emitter regions by implantation through a non-monocrystalline layer 失效通过非单晶层注入制造发射极区域的方法
公开(公告)号：US4452645A
公开(公告)日：1984-06-05
申请号：US242961
申请日：1981-03-12
申请人： Wei-Kan Chu , Ingrid E. Magdo , Hans S. Rupprecht
发明人： Wei-Kan Chu , Ingrid E. Magdo , Hans S. Rupprecht
IPC分类号： H01L21/265 , H01L21/324 , H01L29/08 , H01L21/225
CPC分类号： H01L29/0804 , H01L21/265 , H01L21/324 , Y10S148/039 , Y10S148/047 , Y10S148/117 , Y10S148/124
摘要： A transistor structure is provided with an emitter which is formed from non-monocrystalline silicon which is caused to be converted to monocrystalline silicon during the manufacture of the transistor. In the process of manufacturing the present semiconductor structure, a subcollector is formed in a semiconductor substrate. The subcollector dopant out diffuses into a subsequently deposited epitaxial layer. A base region is formed in the epitaxial layer of a conductivity type opposite that of the conductivity type of the subcollector. This results in a PN junction between the base region and the out diffused subcollector impurities forming the collector of the transistor.A layer of non-monocrystalline silicon is deposited on the epitaxial layer. At least a portion of the non-monocrystalline silicon forms a precursor for an emitter region which is contiguous to but vertically displaced from the surface of the base region. The emitter precursor is then bombarded with ions of a conductivity type that is the same as the conductivity type of the subcollector. The ion bombardment is at a dose and energy level sufficient to displace a portion of the Gaussian distribution of the ions across the interface between the non-monocrystalline layer and the epitaxial layer and into the base region. Thereafter, the structure is annealed by suitable means to drive a portion of the ions deeper into the base region and to convert the non-monocrystalline silicon of the emitter precursor into a monocrystalline emitter region.
摘要翻译： 晶体管结构设置有由非单晶硅形成的发射极，其在晶体管的制造期间被引入单晶硅。 在制造本半导体结构的过程中，在半导体衬底中形成子集电极。 子集电极掺杂剂扩散到随后沉积的外延层中。 在与子集电极的导电类型相反的导电类型的外延层中形成基极区。 这导致形成晶体管的集电极的基极区域和出射扩散的子集电极杂质之间的PN结。 一层非单晶硅沉积在外延层上。 非单晶硅的至少一部分形成与基底区域的表面相邻但垂直移位的发射极区域的前体。 然后用与子集电极的导电类型相同的导电类型的离子轰击发射体前体。 离子轰击处于足以将离子的高斯分布的一部分移动穿过非单晶层和外延层之间的界面并进入基极区域的剂量和能级。 此后，通过合适的方式对该结构进行退火以将一部分离子驱动到基极区域中，并将发射极前体的非单晶硅转换为单晶发射极区域。
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公开(公告)号：US4366493A
公开(公告)日：1982-12-28
申请号：US161611
申请日：1980-06-20
IPC分类号： H01L29/80 , H01L21/28 , H01L21/331 , H01L29/06 , H01L29/201 , H01L29/43 , H01L29/45 , H01L29/73 , H01L29/772 , H01L29/86 , H01L27/12
CPC分类号： H01L29/86 , H01L29/201 , H01L29/452 , H01L29/772
摘要： A semiconductor device of the ballistic type, wherein the carrier transport in the body of the device from one electrode to the other takes place essentially free of collisions, is fabricated with a semiconductor body having a long mean-free path, a body width between ohmic electrodes that is less than or equal to the product of the velocity of a carrier and the time to a collision, but more than the distance that will permit quantum mechanical tunnelling, an impressed voltage less than required for an intervalley carrier transition and having the ohmic external contact on each surface of the body free of any barrier to carrier flow. A ballistic type triode device is provided with a current modulating electrode included within the body of the device. The triode device body is of n type conductivity gallium arsenide containing a zinc doped p type conductivity gallium arsenide current modulating inclusion in the body and having, as at least one ohmic external contact, a graded bandgap indium gallium arsenide region.
摘要翻译： 一种防弹型半导体器件，其中将器件本体中的载体从一个电极输送至另一个电极的载体基本上没有碰撞发生，其半导体本体具有长的无平均通路，欧姆体之间的体宽 电极小于或等于载体速度与碰撞时间的乘积，但大于允许量子力学隧道的距离，外加电压小于间隔载波转换所需的电压，并具有欧姆 身体每个表面上的外部接触没有载体流动的任何障碍。 弹道式三极管装置设置有包括在装置主体内的电流调制电极。 三极管器件本体是n型导电性砷化镓，其含有锌掺杂的p型导电砷化镓电流，其调节包含在体内并具有作为至少一个欧姆外部接触的梯度带隙铟镓砷区域。
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公开(公告)号：US4338138A
公开(公告)日：1982-07-06
申请号：US126611
申请日：1980-03-03
申请人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
发明人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
IPC分类号： H01L21/8222 , H01L21/033 , H01L21/285 , H01L21/331 , H01L21/762 , H01L27/06 , H01L29/73 , H01L29/732 , H01L21/263 , H01L21/203 , H01L21/22 , H01L21/31
CPC分类号： H01L29/66272 , H01L21/033 , H01L21/28525 , H01L21/76229 , H01L21/76232 , H01L29/7325 , Y10S148/131
摘要： An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.
摘要翻译： 一种改进的双极晶体管结构，其形成在第一导电类型的硅衬底的平坦表面上的薄外延层的非常小的区域中，所述薄外延层的非常小的面积具有延伸到所述衬底的平坦表面的垂直侧壁， 所述薄外延层的区域包含按顺序列出的具有暴露平面的第二导电类型的浅深度发射极区域，所述第一导电类型的浅深度基底区域和所述第二导电类型的浅深度有源集电极区域 围绕所述发射极，基极和主动集电极区域的所述第一导电类型的细长区域，所述细长区域包含在所述薄外延层的所述小区域的所述垂直侧壁内并与之共同延伸，由此基极集电极电容由于 到基极 - 集电极结的非常小的区域。 还公开了用于制造改进的双极晶体管结构的工艺和替代工艺。
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公开(公告)号：UST106101I4
公开(公告)日：1985-12-03
申请号：US695657
申请日：1985-01-28
申请人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
发明人： Joseph R. Cavaliere , Cheng T. Horng , Richard R. Konian , Hans S. Rupprecht , Robert O. Schwenker
IPC分类号： H01L21/285 , H01L21/331 , H01L21/762 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/28525 , H01L21/76229 , H01L21/76232 , H01L29/7325
摘要： An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layer containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction.
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公开(公告)号：US4485552A
公开(公告)日：1984-12-04
申请号：US399927
申请日：1982-07-19
申请人： Ingrid E. Magdo , Hans S. Rupprecht
发明人： Ingrid E. Magdo , Hans S. Rupprecht
IPC分类号： H01L21/225 , H01L21/74 , H01L21/82 , H01L27/082 , H01L29/08 , H01L21/22 , H01L21/76
CPC分类号： H01L21/82 , H01L21/225 , H01L21/74 , H01L27/0826 , H01L29/0804
摘要： Disclosed is a method of making on a common substrate complementary vertical NPN and PNP transistors having matched high performance characteristics. A barrier region of a first conductivity type is formed on a semiconductor substrate of a second conductivity type. Then, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate.In a preferred embodiment the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer.
摘要翻译： 公开了一种在公共衬底上制造具有匹配的高性能特性的互补垂直NPN和PNP晶体管的方法。 在第二导电类型的半导体衬底上形成第一导电类型的阻挡区域。 然后，在阻挡区域内形成第二导电类型的互补晶体管之一的集电极区域。 在形成集电极区域的同时在衬底中同时形成第二导电类型的隔离区是方便的。 然后在另一个互补晶体管的衬底中形成第一导电类型的集电极区域。 然后在衬底的表面上形成掺杂有第一导电类型的离子的半导体材料的外延层。 在优选实施例中，PNP晶体管的P型发射极在最后一次驱动处理之前通过在基底的暴露表面上形成多晶硅层而形成。 多晶硅掺杂有P型掺杂剂。 此后，对晶体管结构进行条件，由此将包含在多晶硅层中的掺杂离子驱动到外延层中以提供浅的发射极区域，而不影响外延层的硅晶格中的位错。
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8.发明授权Method of activating implanted impurities in broad area compound semiconductors by short time contact annealing 失效通过短时间接触退火激活广域化合物半导体中的植入杂质的方法
公开(公告)号：US4472206A
公开(公告)日：1984-09-18
申请号：US440655
申请日：1982-11-10
IPC分类号： C30B29/40 , C30B31/22 , H01L21/265 , H01L21/314 , H01L21/324 , H01L21/477
CPC分类号： H01L21/3245 , H01L21/26546 , H01L21/314
摘要： Ion implanted impurity activation in a multi-element compound semiconductor crystal such as gallium arsenide, GaAs, over a broad integrated circuit device area, is accomplished using a short time anneal, in the proximity of a uniform concentration of the most volatile element of said crystal, in solid form, over the broad integrated circuit device area surface. A GaAs integrated circuit wafer having ion implanted impurities in the surface for an integrated circuit is annealed in the vicinity of 800.degree.-900.degree. C. for a time of the order of 1-20 seconds in the proximity of a uniform layer of solid arsenic.
摘要翻译： 在广泛的集成电路器件区域上的多元素化合物半导体晶体（例如砷化镓，GaAs）中的离子注入杂质活化是通过使用短时间退火在所述晶体的最易挥发元素的均匀浓度附近 以固体形式，在广泛的集成电路器件区域表面上。 在集成电路表面上具有离子注入杂质的GaAs集成电路晶片在800-900℃附近在均匀的固体砷层附近退火约1-20秒的时间 。
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9.发明授权
公开(公告)号：US4333227A
公开(公告)日：1982-06-08
申请号：US224705
申请日：1981-01-12
IPC分类号： H01L21/331 , H01L21/74 , H01L21/762 , H01L21/8222 , H01L29/08 , H01L29/10 , H01L29/732 , H01L21/302 , H01L21/31
CPC分类号： H01L29/66272 , H01L21/743 , H01L21/76229 , H01L21/76232 , H01L21/8222 , H01L29/0804 , H01L29/1004 , H01L29/7325 , Y10S148/131 , Y10S438/911 , Y10S438/981
摘要： A method for device fabrication utilizing a self-aligned process. A combination of advanced semiconductor processing techniques including Deep Dielectric Isolation by reactive-ion etching, etching and refilling, planarizing with oxides and resists, and differential thermal oxidation are used to form devices having small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls which extend from the epitaxial silicon surface through the N+ subcollector region into the P substrate. The width of the deep trench is about 2 .mu.m to 3 .mu.m. A shallow oxide trench extends from the epitaxial silicon surface to the upper portion of the N+ subcollector and separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in a low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which is formed by an etch and refill process and which surrounds the emitter and makes lateral contact to the active base.
摘要翻译： 一种利用自对准工艺的器件制造方法。 采用先进的半导体处理技术，包括通过反应离子蚀刻的深层电介质隔离，蚀刻和再填充，用氧化物和抗蚀剂进行平面化以及差示热氧化的先进的半导体处理技术来形成具有小垂直和水平尺寸的器件。 器件区域由深氧化物沟槽围绕，其具有从外延硅表面通过N +子集电极区域延伸到P衬底的几乎垂直的侧壁。 深沟的宽度约为2〜3m。 浅氧化物沟槽从外延硅表面延伸到N +子集电极的上部，并分离基极和集电极触点。 隔离区域和形成晶体管的硅的表面是共面的。 如图所示。 如图1所示，制造的双极晶体管具有台面型结构。 晶体管基极尺寸仅略大于发射极。 这种小的基极面积导致集电极基极电容低，这是超高性能集成电路器件中非常重要的参数。 所公开的结构中与晶体管基极的接触是通过厚度很大的硼掺杂的多晶硅层实现的，该多晶硅层通过蚀刻和再填充工艺形成，并且围绕发射极并与活性基底进行横向接触。
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10.发明授权Annealing of ion implanted III-V compounds in the presence of another III-V 失效在具有较高解离压力的另一种III-V化合物的存在下退火离子注入的III-V化合物
公开(公告)号：US4312681A
公开(公告)日：1982-01-26
申请号：US142916
申请日：1980-04-23
IPC分类号： H01L21/265 , H01L21/324 , H01L21/477
CPC分类号： H01L21/3245 , Y10S148/056 , Y10S148/084
摘要： Practice of the disclosure reduces thermal decomposition and retains stoichiometry during annealing of a multiple element intermetallic semiconductor material by heating it in an environment with an excess of the most volatile constituent. In particular, practice of the disclosure is obtained by annealing a GaAs wafer with a surface into which Si has been implanted while the surface is in proximity to InAs.
摘要翻译： 本公开的实践减少了热分解，并且在多元素金属间半导体材料的退火期间通过在具有过量挥发性成分的环境中加热来保持化学计量。 特别地，本公开的实践是通过在表面接近InAs的情况下将具有Si的表面退火成GaAs晶片获得的。
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