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    Inverse T-gate FET transistor with lightly doped source and drain region
    1.
    发明授权
    Inverse T-gate FET transistor with lightly doped source and drain region 失效
    具有轻掺杂源极和漏极区域的反向T栅极FET晶体管

    公开(公告)号：US5241203A

    公开(公告)日：1993-08-31

    申请号：US824228

    申请日：1992-01-22

    Applicant: Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard ,  Paul J. Tsang

    Inventor： Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard ,  Paul J. Tsang

    IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78

    CPC classification number: H01L29/66606 ,  H01L29/42376 ,  H01L29/7836 ,  H01L2924/0002

    Abstract: A lightly doped drain, field effect transistor with an inverted "T"-gate structure has a gate electrode disposed on a polysilicon pad in a stack opening. The inner edge of a lightly-doped source and drain region is aligned with the gate electrode and its outer edge is aligned with an edge of the polysilicon pad. The inner edge of a heavily-doped source and drain region is aligned with the edge of the edge of the polysilicon pad and its outer edge is aligned with the wall surface that forms the opening. The inner edge of a source and drain contact region is aligned with the wall and extends under the stack.

    Abstract translation: 具有反向“T” - 门结构的轻掺杂漏极场效应晶体管具有设置在堆叠开口中的多晶硅焊盘上的栅电极。 轻掺杂源极和漏极区域的内边缘与栅电极对准，并且其外边缘与多晶硅焊盘的边缘对准。 重掺杂源极和漏极区域的内边缘与多晶硅焊盘的边缘的边缘对准，并且其外边缘与形成开口的壁表面对准。 源极和漏极接触区域的内边缘与壁对准并在堆叠下方延伸。

    Method of forming an inverse T-gate FET transistor
    2.
    发明授权
    Method of forming an inverse T-gate FET transistor 失效
    形成逆T栅极FET晶体管的方法

    公开(公告)号：US5120668A

    公开(公告)日：1992-06-09

    申请号：US727992

    申请日：1991-07-10

    Applicant: Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard ,  Paul J. Tsang

    Inventor： Louis L. Hsu ,  Seiki Ogura ,  Joseph F. Shepard ,  Paul J. Tsang

    IPC: H01L21/336 ,  H01L29/423 ,  H01L29/78

    CPC classification number: H01L29/66606 ,  H01L29/42376 ,  H01L29/7836

    Abstract: A method of forming an LDD field effect transistor with an inverted "T"-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. These conformal layers successively decrease in thickness and are selectively etched in two steps to form a self-aligned inverted T structure. A first reactive ion etch (RIE) step preferentially etches the exposed outer polysilicon to a certain depth. During a second step RIE the polysilicon layer is completely etched down to the a gate oxide surface and the metal layer is preferentially etched so that subtends only the remaining nitride or oxide cap.

    Method of fabricating an MOS dynamic RAM with lightly doped drain
    3.
    发明授权
    Method of fabricating an MOS dynamic RAM with lightly doped drain 失效
    制造具有轻掺杂漏极的MOS动态RAM的方法

    公开(公告)号：US4366613A

    公开(公告)日：1983-01-04

    申请号：US217497

    申请日：1980-12-17

    Applicant: Seiki Ogura ,  Paul J. Tsang

    Inventor： Seiki Ogura ,  Paul J. Tsang

    IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/08 ,  H01L29/78 ,  H01L21/26

    CPC classification number: H01L27/10873 ,  H01L29/0847 ,  H01L29/78

    Abstract: A method of manufacturing LDD MOS FET RAM capable of delineating short (less than 1 micrometer) lightly doped drain regions. An N.sup.- implant is effected between gate electrodes and field oxide insulators, before the N.sup.+ implant. An insulator layer is then deposited also prior to N.sup.+ ion implantation. Reactive ion etching of the layer leaves narrow dimensioned insulator regions adjacent the gate electrode which serves to protect portions of the N.sup.- impurity region during the subsequent N.sup.+ implant. These protected regions are the lightly doped source/drain regions.

    Abstract translation: 一种制造能够描绘短（小于1微米）轻掺杂漏极区的LDD MOS FET RAM的方法。 在N +植入之前，在栅电极和场氧化物绝缘体之间进行N-注入。 然后在N +离子注入之前也沉积绝缘体层。 层的反应离子蚀刻离开邻近栅极的窄尺寸绝缘体区域，其用于在随后的N +植入期间保护N杂质区域的部分。 这些受保护区域是轻掺杂的源极/漏极区域。

    Process of making BiCMOS devices having closely spaced device regions
    4.
    发明授权
    Process of making BiCMOS devices having closely spaced device regions 失效
    制造具有紧密间隔的器件区域的BiCMOS器件的工艺

    公开(公告)号：US5015594A

    公开(公告)日：1991-05-14

    申请号：US261952

    申请日：1988-10-24

    Applicant: Shao-Fu S. Chu ,  San-Mei Ku ,  Russell C. Lange ,  Joseph F. Shephard ,  Paul J. Tsang ,  Wen-Yuan Wang

    Inventor： Shao-Fu S. Chu ,  San-Mei Ku ,  Russell C. Lange ,  Joseph F. Shephard ,  Paul J. Tsang ,  Wen-Yuan Wang

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/60 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

    CPC classification number: H01L21/76897 ,  H01L21/8249 ,  Y10S148/009

    Abstract: A method of forming a semiconductor device on a body of semiconductor material having a first doped region of a first conductivity type, comprising the steps of: forming a stud over the first doped region; using the stud as a mask to form a second doped region of a second conductivity type in the surface of the first doped region adjoining the stud; forming a sidewall of insulating material on the stud; forming a first device contact within the sidewall; and forming a second device contact over the second doped region adjoining the sidewall, such that the first and second electrical contacts are separated by the sidewall.In accordance with an embodiment of the present invention, the step of forming the second device contact includes the steps of forming a layer of conductive material generally conformally over the first doped region and the stud, and then planarizing the layer of conductive material to a height equal to or less than that of the sidewalls. The second contact is thus self-aligned with the first and second doped regions and the first device contact.The method of the present invention can be utilized to fabricate bipolar transistors, insulated gate transistors, and BICMOS logic including both types of transistors. It can further be used to fabricate any other type of semiconductor device which utilizes the self-aligned, closely spaced device regions and contacts of the present invention.

    Method for forming recessed regions of thermally oxidized silicon and structures thereof utilizing anisotropic etching
    6.
    发明授权
    Method for forming recessed regions of thermally oxidized silicon and structures thereof utilizing anisotropic etching 失效
    利用各向异性蚀刻形成热氧化硅的凹陷区域及其结构的方法

    公开(公告)号：US3998674A

    公开(公告)日：1976-12-21

    申请号：US634571

    申请日：1975-11-24

    Applicant: Donald P. Cameron ,  Paul J. Tsang

    Inventor： Donald P. Cameron ,  Paul J. Tsang

    IPC: H01L21/76 ,  H01L21/306 ,  H01L21/32 ,  H01L21/762 ,  H01L21/20

    CPC classification number: H01L21/76202 ,  H01L21/30608 ,  H01L21/32 ,  Y10S438/973

    Abstract: An improved method for forming a recessed thermal SiO.sub.2 isolation region in a monocrystalline silicon semiconductor body having a major surface lying in a (100) plane as defined by the Miller indices by forming an etch resistant and oxidation resistant masking layer on the major surface of the body, forming at least one rectilinear annular opening in the masking layer, the opening being oriented with the sides parallel to the [100] directions on the major surface, removing a portion of the exposed body by anisotropic chemical etching, and oxidizing the resultant exposed portions of the body until the surface of the resultant SiO.sub.2 and major surface are substantially coplanar.A semiconductor device including a silicon substrate of a first conductivity, the major surface being in the (100) plane, an epitaxial silicon layer on the substrate, a lateral PN junction in the substrate, at least one annular rectangular shaped recessed SiO.sub.2 region in the epitaxial layer extending inwardly to the PN junction, the annular region being oriented with the sides parallel to the [100] direction on the major surface.

    Abstract translation: 一种用于在单晶硅半导体器件中形成凹陷的热二氧化硅隔离区域的改进方法，其具有位于（100）平面中的主要表面，如由米勒指数所限定的，其在主表面上形成耐蚀刻和抗氧化掩蔽层 在掩模层中形成至少一个直线环形开口，该开口在主表面上平行于[100]方向取向，通过各向异性化学蚀刻去除一部分暴露体，并将所得暴露 直到所得SiO 2和主表面的表面基本上共面为止。

    Bipolar transistor
    8.
    发明授权
    Bipolar transistor 失效
    双极晶体管

    公开(公告)号：US4392149A

    公开(公告)日：1983-07-05

    申请号：US273705

    申请日：1981-06-15

    Applicant: Cheng T. Horng ,  Robert O. Schwenker ,  Paul J. Tsang

    Inventor： Cheng T. Horng ,  Robert O. Schwenker ,  Paul J. Tsang

    IPC: H01L21/033 ,  H01L21/331 ,  H01L21/8222 ,  H01L29/08 ,  H01L29/732 ,  H01L27/12

    CPC classification number: H01L29/66272 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/8222 ,  H01L29/0804 ,  H01L29/7325

    Abstract: Disclosed is a self-aligned process for providing an improved bipolar transistor structure.The process includes the chemically etching of an intermediate insulating layer to undercut another top layer of a different insulating material in a self-aligned emitter process wherein the spacing of the emitter contact to the polysilicon base contact is reduced to a magnitude of approximately 0.2 to 0.3 micrometers. In addition, in the process an emitter plug is formed to block the emitter region from the heavy P+ ion dose implant of the extrinsic base.

    Abstract translation: 公开了一种用于提供改进的双极晶体管结构的自对准工艺。 该方法包括中间绝缘层的化学蚀刻，以在自对准发射极工艺中切割出不同绝缘材料的另一顶层，其中发射极接触与多晶硅基底接触的间隔减小到约0.2至0.3的量级 微米。 此外，在该过程中，形成发射极插塞以阻挡来自外部基极的重P +离子剂量植入物的发射极区域。

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