A method of manufacturing LDD MOS FET RAM capable of delineating short (less than 1 micrometer) lightly doped drain regions. An N.sup.- implant is effected between gate electrodes and field oxide insulators, before the N.sup.+ implant. An insulator layer is then deposited also prior to N.sup.+ ion implantation. Reactive ion etching of the layer leaves narrow dimensioned insulator regions adjacent the gate electrode which serves to protect portions of the N.sup.- impurity region during the subsequent N.sup.+ implant. These protected regions are the lightly doped source/drain regions.