Simplified twin monos fabrication method with three extra masks to standard CMOS

Invention Grant

US06838344B2 Simplified twin monos fabrication method with three extra masks to standard CMOS 有权

Title translation: 简单的双胞胎制造方法，具有三个额外的掩码到标准CMOS

Please log in to see more content

Patent Title: Simplified twin monos fabrication method with three extra masks to standard CMOS
Patent Title (中): 简单的双胞胎制造方法，具有三个额外的掩码到标准CMOS
Application No.: US10853453

Application Date: 2004-05-25
Publication No.: US06838344B2

Publication Date: 2005-01-04
Inventor: Kimihiro Satoh , Tomoya Saito , Seiki Ogura
Applicant: Kimihiro Satoh , Tomoya Saito , Seiki Ogura
Applicant Address: US OR Hillsboro
Assignee: Halo LSI, Inc.
Current Assignee: Halo LSI, Inc.
Current Assignee Address: US OR Hillsboro
Agent George O. Saile; Stephen B. Ackerman; Rosemary L. S. Pike
Main IPC: H01L21/8246
IPC: H01L21/8246 ; H01L27/115 ; H01L21/336

Simplified twin monos fabrication method with three extra masks to standard CMOS

Abstract:

The invention proposes to simplify fabrication of the twin MONOS memory array. The twin MONOS memory array can be embedded into a standard CMOS circuit by the process of the present invention by adding only three additional mask levels. Conventional floating gate devices need ten or more extra masks. In the present invention, the unique twin MONOS process steps can be inserted into the standard CMOS process flow without any parameter modifications. The present invention also achieves increased endurance by means of reducing the widths of the sidewall control gate and underlying nitride storage region.

Abstract(Chinese):

本发明提出简化双MONOS存储器阵列的制造。通过仅添加三个附加掩模级别，本发明的双MONOS存储器阵列可以嵌入到标准CMOS电路中。常规浮动栅极器件需要十个或更多个额外的掩模。在本发明中，独特的双MONOS工艺步骤可以插入到标准CMOS工艺流程中，无需任何参数修改。本发明还通过减小侧壁控制栅极和下面的氮化物存储区域的宽度来实现增加的耐久性。

Public/Granted literature

US20040219751A1 Simplified twin monos fabrication method with three extra masks to standard CMOS Public/Granted day:2004-11-04

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8246	.........只读存储器结构（ROM）