公开(公告)号：US12176294B2

公开(公告)日：2024-12-24

申请号：US18339137

申请日：2023-06-21

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: A bonded structure is disclosed. The bonded structure can include an interconnect structure that has a first side and a second side opposite the first side. The bonded structure can also include a first die that is mounted to the first side of the interconnect structure. The first die can be directly bonded to the interconnect structure without an intervening adhesive. The bonded structure can also include a second die that is mounted to the first side of the interconnect structure. The bonded structure can further include an element that is mounted to the second side of the interconnect structure. The first die and the second die are electrically connected by way of at least the interconnect structure and the element.

公开(公告)号：US20240387322A1

公开(公告)日：2024-11-21

申请号：US18235271

申请日：2023-08-17

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Gaius Gillman Fountain Jr. ,  Belgacem Haba ,  Kyong-Mo Bang

IPC: H01L23/473 ,  H01L21/48 ,  H01L23/00 ,  H01L23/427 ,  H01L23/467 ,  H01L25/18 ,  H10B80/00

Abstract: A device package comprising an integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises a top portion and a bottom portion horizontally adjacent to the top portion. The top portion comprises upper cavity dividers extending downwardly to define upper cavity volumes. The bottom portion comprises lower cavity dividers extending upwardly to define lower cavity volumes. The upper cavity dividers and the lower cavity dividers alternate across a horizontal length of the cold plate.

公开(公告)号：US20240332184A1

公开(公告)日：2024-10-03

申请号：US18345607

申请日：2023-06-30

Applicant: Adeia Semiconductor Bonding Technologies, Inc.

Inventor： Rajesh Katkar ,  Belgacem Haba

IPC: H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/535

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/535

Abstract: Integrated circuits and method of making including a plurality of transistors, each of the transistors including a source, a drain, and a channel located between the source and the drain. The integrated circuit also includes a plurality of buried power rails including a plurality of VSS power rails and a plurality of VDD power rails, at least one VSS pad and at least one VDD pad, a plurality of vias electrically connecting the at least one VSS pad to at least two of the plurality of VSS power rails, and a plurality of vias electrically connecting the at least one VDD pad to at least two of the plurality of buried VDD power rails.

公开(公告)号：US20240332129A1

公开(公告)日：2024-10-03

申请号：US18620753

申请日：2024-03-28

Applicant: Adeia Semiconductor Bonding Technologies Inc

Inventor： Belgacem Haba ,  Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/46 ,  H01L23/00 ,  H01L23/24 ,  H01L23/498

CPC classification number: H01L23/46 ,  H01L23/49822 ,  H01L24/08 ,  H01L23/24 ,  H01L2224/08225

Abstract: The present disclosure provides for integrated cooling systems including backside power delivery and methods of manufacturing the same. An integrated cooling assembly may include a device and a cold plate. The cold plate has a first side and an opposite second side, the first side having a recessed surface, sidewalls around the recessed surface that extend downwardly therefrom to define a cavity, and a plurality of support features disposed in the cavity. The first side of the cold plate is attached to a backside of the device to define a coolant channel therebetween. The cold plate includes a substrate, a dielectric layer disposed on a first surface of the substrate, a first conductive layer disposed between the first surface and the dielectric layer, a second conductive layer disposed on a second surface of the substrate, and thru-substrate interconnects connecting the first conductive layer to the second conductive layer.

公开(公告)号：US20240332128A1

公开(公告)日：2024-10-03

申请号：US18129567

申请日：2023-03-31

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Cyprian Emeka Uzoh ,  Belgacem Haba ,  Rajesh Katkar

IPC: H01L23/46 ,  H01L23/367 ,  H01L23/433

CPC classification number: H01L23/46 ,  H01L23/367 ,  H01L23/433

Abstract: Embodiments herein provide for device packages comprising an integrated cooling assembly and methods of cooling packaged devices. The integrated cooling assembly comprising a semiconductor device, a manifold attached to the semiconductor device, and a sonic transducer attached to the manifold. The manifold comprises a top portion and a waveguide extending downwardly from the top portion. The sonic transducer is attached to the top portion. The top portion, the waveguide, and a backside of the semiconductor device collectively define a coolant chamber volume therebetween.

公开(公告)号：US12057383B2

公开(公告)日：2024-08-06

申请号：US18148001

申请日：2022-12-29

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Rajesh Katkar ,  Gabriel Z. Guevara ,  Javier A. DeLaCruz ,  Shaowu Huang ,  Laura Willis Mirkarimi

IPC: H01L23/498 ,  H01G2/02 ,  H01G4/12 ,  H01G4/228 ,  H01G4/30 ,  H01G4/38 ,  H01G4/40 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/66 ,  H05K1/18 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01G2/02 ,  H01G4/1245 ,  H01G4/228 ,  H01G4/30 ,  H01G4/40 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L24/08 ,  H01L24/32 ,  H05K1/18 ,  H01G4/38 ,  H01L23/49816 ,  H01L23/66 ,  H01L24/05 ,  H01L24/80 ,  H01L2223/6666 ,  H01L2223/6672 ,  H01L2224/03845 ,  H01L2224/05005 ,  H01L2224/05017 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05576 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/0807 ,  H01L2224/08265 ,  H01L2224/16265 ,  H01L2224/32265 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19103 ,  H05K1/0231 ,  H05K1/185 ,  H05K2201/10015 ,  H01L2224/80203 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05686 ,  H01L2924/05442 ,  H01L2224/80948 ,  H01L2924/00014 ,  H01L2224/05556 ,  H01L2924/00012

Abstract: In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

公开(公告)号：US12046569B2

公开(公告)日：2024-07-23

申请号：US18295776

申请日：2023-04-04

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Belgacem Haba

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/08 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.

公开(公告)号：US11916054B2

公开(公告)日：2024-02-27

申请号：US17586236

申请日：2022-01-27

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Paul M. Enquist ,  Belgacem Haba

IPC: H01L25/18 ,  H01L27/146 ,  H01L21/822 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/09 ,  H01L25/074 ,  H01L25/50 ,  H01L27/1469 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14687 ,  H01L2224/02379 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Stacked devices and methods of fabrication are provided. Die-to-wafer (D2W) direct-bonding techniques join layers of dies of various physical sizes, form factors, and foundry nodes to a semiconductor wafer, to interposers, or to boards and panels, allowing mixing and matching of variegated dies in the fabrication of 3D stacked devices during wafer level packaging (WLP). Molding material fills in lateral spaces between dies to enable fan-out versions of 3D die stacks with fine pitch leads and capability of vertical through-vias throughout. Molding material is planarized to create direct-bonding surfaces between multiple layers of the variegated dies for high interconnect density and reduction of vertical height. Interposers with variegated dies on one or both sides can be created and bonded to wafers. Logic dies and image sensors from different fabrication nodes and different wafer sizes can be stacked during WLP, or logic dies and high bandwidth memory (HBM) of different geometries can be stacked during WLP.

公开(公告)号：US11842894B2

公开(公告)日：2023-12-12

申请号：US17129632

申请日：2020-12-21

Applicant: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

Inventor： Rajesh Katkar ,  Belgacem Haba

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/06 ,  H01L24/26 ,  H01L24/93

Abstract: An element that is configured to bond to another element is disclosed. A first element that can include a first plurality of contact pads on a first surface. The first plurality of contact pads includes a first contact pad and a second contact pad that are spaced apart from one another. The first and second contact pads are electrically connected to one another for redundancy. The first element can be prepared for direct bonding. The first element can be bonded to a second element to form a bonded structure. The second element has a second plurality of contact pads on a second surface. At least one of the second plurality of contact pads is bonded and electrically connected to at least one of the first plurality of contact pads.

公开(公告)号：US20230317628A1

公开(公告)日：2023-10-05

申请号：US18087705

申请日：2022-12-22

Applicant: Adeia Semiconductor Bonding Technologies Inc.

Inventor： Belgacem Haba ,  Javier A. DeLaCruz ,  Rajesh Katkar ,  Arkalgud R. Sitaram

IPC: H01L23/552 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/573 ,  H01L24/05 ,  H01L24/83 ,  H01L24/29 ,  H01L2224/83896

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry and a first bonding layer. The bonded structure can include a protective element directly bonded to the semiconductor element without an adhesive along a bonding interface. The protective element can include an obstructive material disposed over the active circuitry and a second bonding layer on the obstructive material. The second bonding layer can be directly bonded to the first bonding layer without an adhesive. The obstructive material can be configured to obstruct external access to the active circuitry.