公开(公告)号：US12063794B2

公开(公告)日：2024-08-13

申请号：US17334810

申请日：2021-05-31

Applicant: Southern University of Sciene and Technology

Inventor： Guobiao Zhang

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/84 ,  H10B63/20 ,  H10N70/841 ,  H10N70/063

Abstract: High-density three-dimensional (3-D) vertical memory (3D-MV) includes lightly-doped-segment (LDS) 3D-MV and non-circular-hole (NCH) 3D-MV. The preferred LDS 3D-MV takes advantage of longitudinal space, instead of lateral space, to guarantee normal write operation. On the other hand, the lateral cross-section of the memory hole of the preferred NCH 3D-MV includes at least two intersecting pairs of parallel sides, with each pair formed through a single DUV exposure and having a minimum spacing

公开(公告)号：US12058943B2

公开(公告)日：2024-08-06

申请号：US18105935

申请日：2023-02-06

Applicant: International Business Machines Corporation

Inventor： Nanbo Gong ,  Guy M. Cohen ,  Takashi Ando

IPC: H10N70/20 ,  G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10N70/8413 ,  G11C2013/008

Abstract: An apparatus comprises a phase-change material, a first electrode at a first end of the phase-change material, a second electrode at a second end of the phase-change material, and a heating element coupled to a least a given portion of the phase-change material between the first end and the second end. The apparatus also comprises a first input terminal coupled to the heating element, a second input terminal coupled to the heating element, and an output terminal coupled to the second electrode.

公开(公告)号：US12052876B2

公开(公告)日：2024-07-30

申请号：US17549162

申请日：2021-12-13

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  WEEBIT NANO LTD

Inventor： Anthonin Verdy ,  Gabriel Molas ,  Paola Trotti ,  Amir Regev

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10B63/84 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  H10N70/821

Abstract: A memory includes a matrix of resistive memory cells and an interfacing device to interface the matrix, the interfacing device including at least a conversion capacitor, an electric source, a first switch and a second switch, the interfacing device being configured to: a) connect the conversion capacitor to the source by the second switch to charge the conversion capacitor, then, b) disconnect the conversion capacitor from the source and connect the conversion capacitor to the matrix to achieve a conversion between, on the one hand, a resistive state of one of the memory cells of the matrix, and, on the other hand, a state of charge of the conversion capacitor.

公开(公告)号：US20240251687A1

公开(公告)日：2024-07-25

申请号：US18590813

申请日：2024-02-28

Applicant: SK hynix Inc.

Inventor： Myoung Sub KIM ,  Tae Hoon KIM ,  Beom Seok LEE ,  Seung Yun LEE ,  Hwan Jun ZANG ,  Byung Jick CHO ,  Ji Sun HAN

IPC: H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20

CPC classification number: H10N70/841 ,  H10B61/00 ,  H10B63/84 ,  H10N50/01 ,  H10N50/80 ,  H10N70/011 ,  H10N70/231

Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.

公开(公告)号：US20240251557A1

公开(公告)日：2024-07-25

申请号：US18623909

申请日：2024-04-01

Applicant: SK hynix Inc.

Inventor： Jin Ha KIM

IPC: H10B43/27 ,  H10B41/27 ,  H10B63/00

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B63/845

Abstract: A semiconductor device includes a stacked structure including conductive layers and insulating layers alternately stacked with each other, and a channel layer passing through the stacked structure, wherein the channel layer is a single layer, the single layer including a first GIDL region, a cell region, and a second GIDL region, and the first GIDL region has a greater thickness than each of the cell region and the second GIDL region.

公开(公告)号：US12048160B2

公开(公告)日：2024-07-23

申请号：US18186062

申请日：2023-03-17

Applicant: SK hynix Inc.

Inventor： Changhan Kim ,  In Ku Kang ,  Sun Young Kim

IPC: H10B43/27 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B43/27 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35 ,  H10B63/845 ,  H10N70/066 ,  H10N70/231

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

公开(公告)号：US12041860B2

公开(公告)日：2024-07-16

申请号：US17581153

申请日：2022-01-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Der Chih ,  Wen-Zhang Lin ,  Yun-Sheng Chen ,  Jonathan Tsung-Yung Chang ,  Chrong-Jung Lin ,  Ya-Chin King ,  Cheng-Jun Lin ,  Wang-Yi Lee

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/841

Abstract: A resistive memory device includes a bottom electrode, a top electrode and a resistance changing element. The top electrode is disposed above and spaced apart from the bottom electrode, and has a downward protrusion aligned with the bottom electrode. The resistance changing element covers side and bottom surfaces of the downward protrusion.

公开(公告)号：US20240237566A1

公开(公告)日：2024-07-11

申请号：US18443283

申请日：2024-02-15

Applicant: IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)

Inventor： Jea Gun PARK ,  Dae Seong WOO ,  Soo Min JIN ,  Sang Hong PARK ,  Sung Mok JUNG

IPC: H10N70/00 ,  G06N3/063 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8845 ,  G06N3/063 ,  H10B63/80 ,  H10N70/026 ,  H10N70/24 ,  H10N70/841

Abstract: Disclosed is an artificial synapse device including an amorphous carbon oxide-based resistance change memory device and a method of fabricating the same, and more particularly to a technology for providing an artificial synapse device capable of implementing the characteristics of biological synapses responsible for memory and information transfer in the human brain using a resistance change memory device. More particularly, the artificial synapse device according to an embodiment of the provided includes a first electrode; a second electrode disposed to face the first electrode; and a switching layer formed of an amorphous carbon oxide deposited by injecting oxygen when sputtering carbon into a target between the first electrode and the second electrode, wherein the artificial synapse device has synaptic characteristics wherein a value of an output current changes gradually when a same voltage of either set voltage or reset voltage is repeatedly applied to the first electrode.

公开(公告)号：US20240237359A1

公开(公告)日：2024-07-11

申请号：US18152072

申请日：2023-01-09

Applicant: TetraMem Inc.

Inventor： Ning Ge ,  Minxian Zhang ,  Mingche Wu ,  Gary Miner

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  H10B63/30 ,  H10N70/063 ,  H10N70/253 ,  H10N70/841 ,  H10N70/8833

Abstract: An apparatus including a plurality of resistive random-access memory (RRAM) devices is provided. The RRAM devices are fabricated on a single substrate in some embodiments. The apparatus includes an interconnect layer fabricated on the substrate. A first RRAM device of the RRAM devices includes a first bottom electrode, a first top electrode; and a first filament-forming layer fabricated between the first bottom electrode and the first top electrode. A second RRAM device of the RRAM devices includes a second bottom electrode, a second top electrode, and a second filament-forming layer fabricated between the second bottom electrode and the second top electrode. The first bottom electrode and the second bottom electrode are fabricated on multiple metallic pads or metallic vias of the interconnect layer. The first filament-forming layer and the second filament-forming layer include different switching oxides.

公开(公告)号：US20240237357A1

公开(公告)日：2024-07-11

申请号：US18615936

申请日：2024-03-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jheng-Hong JIANG ,  Cheung CHENG ,  Chia-Wei LIU

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00

CPC classification number: H10B63/20 ,  G11C13/0026 ,  G11C13/0028 ,  H10B63/84 ,  H10N70/021 ,  H10N70/023 ,  H10N70/063 ,  H10N70/066 ,  H10N70/826 ,  H10N70/841 ,  H10N70/881 ,  H10N70/8833

Abstract: A memory device includes: a first conductor extending in parallel with a first axis; a first selector material comprising a first portion that extends along a first sidewall of the first conductor; a second selector material comprising a first portion that extends along the first sidewall of the first conductor; a first variable resistive material comprising a portion that extends along the first sidewall of the first conductor; and a second conductor extending in parallel with a second axis substantially perpendicular to the first axis, wherein the first portion of the first selector material, the first potion of the second selector material, and the portion of the first variable resistive material are arranged along a first direction in parallel with a third axis substantially perpendicular to the first axis and second axis.