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公开(公告)号：US4836886A
公开(公告)日：1989-06-06
申请号：US123639
申请日：1987-11-23
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/3213
CPC分类号： H01L21/32137 , H01L21/3065 , H01L21/32136
摘要： A plasma comprised of trifluorochloromethane and an oxidant etches non-insulating materials such as tungsten at very high etch rates when the oxidant comprises at least 50% of the plasma by volume.
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72.发明授权公开(公告)号：US09000585B2
公开(公告)日：2015-04-07
申请号：US13344628
申请日：2012-01-06
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05006 , H01L2224/05093 , H01L2224/05567 , H01L2224/05571 , H01L2224/10122 , H01L2224/10126 , H01L2224/13006 , H01L2224/13022 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2224/05552
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.
摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。 该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。 还提供了一种方法和结构。
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73.发明授权System and method for forming aluminum fuse for compatibility with copper BEOL interconnect scheme 有权用于形成铝保险丝的系统和方法，用于与铜BEOL互连方案兼容公开(公告)号：US08921975B2
公开(公告)日：2014-12-30
申请号：US13488870
申请日：2012-06-05
申请人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
发明人： Felix P. Anderson , Timothy H. Daubenspeck , Jeffrey P. Gambino , Timothy S. Hayes , Donald R. Letourneau , Thomas L. McDevitt , Anthony K. Stamper
IPC分类号： H01L21/768 , H01L23/525
CPC分类号： H01L21/76892 , H01L21/76838 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.
摘要翻译： 一种半导体熔丝器件和一种制造熔丝器件的方法，该熔丝器件包括最后的金属互连层，其包括至少两个分立的金属导体，沉积在最后的金属互连层和至少两个分立的金属导体上的层间电介质层， 连接至少两个分立的金属导体的线铝保险丝，以及铝保险丝上方的保险丝开口。
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公开(公告)号：US08916463B2
公开(公告)日：2014-12-23
申请号：US13604878
申请日：2012-09-06
CPC分类号： H01L23/481 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05624 , H01L2224/061 , H01L2224/45144 , H01L2224/45147 , H01L2224/48453 , H01L2224/48463 , H01L2224/48624 , H01L2224/48824 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A splash containment structure for semiconductor structures and associated methods of manufacture are provided. A method includes: forming wire bond pads in an integrated circuit chip and forming at least one passivation layer on the chip. The at least one passivation layer includes first areas having a first thickness and second areas having a second thickness. The second thickness is greater than the first thickness. The first areas having the first thickness extend over a majority of the chip. The second areas having the second thickness are adjacent the wire bond pads.
摘要翻译： 提供了一种用于半导体结构和相关制造方法的防溅结构。 一种方法包括：在集成电路芯片中形成引线接合焊盘并在芯片上形成至少一个钝化层。 所述至少一个钝化层包括具有第一厚度的第一区域和具有第二厚度的第二区域。 第二厚度大于第一厚度。 具有第一厚度的第一区域延伸超过芯片的大部分。 具有第二厚度的第二区域与引线接合焊盘相邻。
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公开(公告)号：US08710656B2
公开(公告)日：2014-04-29
申请号：US13553882
申请日：2012-07-20
申请人： Timothy H. Daubenspeck , Brian M. Erwin , Jeffrey P. Gambino , Wolfgang Sauter , George J. Scott
发明人： Timothy H. Daubenspeck , Brian M. Erwin , Jeffrey P. Gambino , Wolfgang Sauter , George J. Scott
CPC分类号： H01L23/3192 , H01L23/525 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/02375 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05093 , H01L2224/05124 , H01L2224/05147 , H01L2224/05569 , H01L2224/05572 , H01L2224/0603 , H01L2224/0614 , H01L2224/1146 , H01L2224/1147 , H01L2224/13027 , H01L2224/131 , H01L2224/14104 , H01L2224/14131 , H01L2924/00014 , H01L2924/3512 , H01L2924/00012 , H01L2924/014 , H01L2224/05552
摘要： An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump.
摘要翻译： 公开了一种集成电路（IC）芯片，其包括在后端（BEOL）层中的多个金属垂直互连访问（通孔），BEOL层上的再分配层（RDL），BEOL层具有多个键 焊盘，每个接合焊盘通过RDL连接到至少一个对应的金属通孔; 以及连接到每个接合焊盘的焊料凸块，其中每个焊料凸块横向偏离连接到所述接合焊盘的相应金属通孔朝向所述IC芯片的中心偏移距离，其中所述偏移距离在所述IC 芯片。 在一个实施例中，每个焊料凸块的偏移距离与IC芯片的中心与该焊料凸块的相应焊料凸块焊盘结构的中心之间的距离成比例。
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76.发明授权Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof 有权用于焊料凸块的阻挡层冶金的底切修复及其方法公开(公告)号：US08298930B2
公开(公告)日：2012-10-30
申请号：US12959697
申请日：2010-12-03
申请人： Charles L. Arvin , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
发明人： Charles L. Arvin , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L23/488
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/02126 , H01L2224/0361 , H01L2224/0382 , H01L2224/03912 , H01L2224/10126 , H01L2224/1147 , H01L2224/1182 , H01L2224/11912 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01074 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material.
摘要翻译： 制造半导体结构的方法包括图案化在焊料材料下形成底切的阻挡层冶金（BLM），以及在底切和焊料材料上形成修复材料。 该方法还包括从焊料材料中去除修复材料，以及回流焊料。
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公开(公告)号：US20120220117A1
公开(公告)日：2012-08-30
申请号：US13463855
申请日：2012-05-04
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sulliwan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sulliwan
IPC分类号： H01L21/283
CPC分类号： H01L23/49816 , H01L23/49811 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/83 , H01L24/90 , H01L2224/0401 , H01L2224/0603 , H01L2224/06505 , H01L2224/11822 , H01L2224/13082 , H01L2224/131 , H01L2224/1319 , H01L2224/1329 , H01L2224/133 , H01L2224/14 , H01L2224/1403 , H01L2224/14505 , H01L2224/16 , H01L2224/17051 , H01L2224/81136 , H01L2224/81191 , H01L2224/81193 , H01L2224/81801 , H01L2224/83191 , H01L2224/83194 , H01L2224/838 , H01L2924/00013 , H01L2924/01013 , H01L2924/01022 , H01L2924/01033 , H01L2924/01074 , H01L2924/01076 , H01L2924/01082 , H01L2924/014 , H01L2924/12044 , H01L2924/14 , H05K3/303 , H05K3/3436 , H05K2201/0379 , H05K2201/10674 , H05K2201/2036 , Y02P70/613 , H01L2924/00014 , H01L2224/13099 , H01L2924/3512 , H01L2924/00
摘要： A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are similar in size to the first solder balls, on the corresponding surface of the package substrate to which the chip will be attached. Then, the method positions the surface of the semiconductor chip next to the corresponding surface of the package substrate. The adhesive bonds the distal ends of the polymer pillars to the corresponding surface of the package substrate. The method heats the first solder balls and the second solder balls to join the first solder balls and the second solder balls into solder pillars.
摘要翻译： 将芯片与芯片载体，陶瓷封装等（封装基板）连接的方法比半导体芯片表面上的通常的第一焊球和聚合物柱形成更小，并且将粘合剂施加到聚合物柱的远端。 该方法还形成与芯片将附接到的封装衬底的相应表面上尺寸相似的第二焊球。 然后，该方法将半导体芯片的表面定位在封装衬底的相应表面的旁边。 粘合剂将聚合物柱的末端粘合到包装基底的相应表面上。 该方法加热第一焊球和第二焊球以将第一焊球和第二焊球接合成焊料柱。
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公开(公告)号：US20120119362A1
公开(公告)日：2012-05-17
申请号：US12948092
申请日：2010-11-17
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/11 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/0401 , H01L2224/05556 , H01L2224/061 , H01L2224/0613 , H01L2224/13006 , H01L2224/13111 , H01L2224/13116 , H01L2924/0001 , H01L2924/01005 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/12044 , H01L2224/13099 , H01L2924/00 , H01L2924/00012
摘要： A structure and a method of manufacturing a Pb-free Controlled Collapse Chip Connection (C4) with a Ball Limiting Metallurgy (BLM) structure for semiconductor chip packaging that reduce chip-level cracking during the Back End of Line (BEOL) processes of chip-join cool-down. An edge of the BLM structure that is subject to tensile stress during chip-join cool down is protected from undercut of a metal seed layer, caused by wet etch of the chip to remove metal layers from the chip's surface and solder reflow, by an electroplated barrier layer, which covers a corresponding edge of the metal seed layer.
摘要翻译： 用于半导体芯片封装的具有球限制冶金（BLM）结构的无铅控制崩溃芯片连接（C4）的结构和方法，其在芯片级后端（BEOL）工艺中减少芯片级开裂， 加入冷却。 在芯片连接冷却期间受到拉伸应力的BLM结构的边缘被保护以防止金属种子层的底切，由芯片的湿法蚀刻引起，以通过电镀从芯片的表面和焊料回流中去除金属层 阻挡层，其覆盖金属种子层的相应边缘。
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公开(公告)号：US08164188B2
公开(公告)日：2012-04-24
申请号：US12624065
申请日：2009-11-23
IPC分类号： H01L21/02 , H01L21/60 , H01L23/48 , H01L23/485
CPC分类号： H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03462 , H01L2224/0347 , H01L2224/0361 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05027 , H01L2224/05073 , H01L2224/05166 , H01L2224/05184 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/11334 , H01L2224/1147 , H01L2224/11849 , H01L2224/11912 , H01L2224/13006 , H01L2224/131 , H01L2924/00013 , H01L2924/0002 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/181 , H01L2924/00014 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2224/05552 , H01L2924/00
摘要： A method comprises depositing a first metal containing layer into a trench structure, which contacts a metalized area of a semiconductor structure. The method further includes patterning at least one opening in a resist to the first metal containing layer. The opening should be in alignment with the trench structure. At least a pad metal containing layer is formed within the at least one opening (preferably by electroplating processes). The resist and the first metal layer underlying the resist are then etched (with the second metal layer acting as a mask, in embodiments). The method includes flowing solder material within the trench and on pad metal containing layer after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.
摘要翻译： 一种方法包括将第一含金属层沉积到与半导体结构的金属化区域接触的沟槽结构中。 该方法还包括将抗蚀剂中的至少一个开口图案化为第一含金属层。 开口应与沟槽结构对齐。 在至少一个开口内（优选通过电镀工艺）形成至少一垫层金属层。 然后蚀刻抗蚀剂和抗蚀剂下面的第一金属层（在实施例中第二金属层用作掩模）。 该方法包括在蚀刻工艺之后使沟槽内的焊料材料和含焊垫金属的层流动。 该结构是受控的崩溃芯片连接（C4）结构，包括至少一个以抗蚀剂图案形成的电镀金属层，以形成至少一个球限制冶金层。 该结构还包括没有底切的底层金属层。
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公开(公告)号：US20110133307A1
公开(公告)日：2011-06-09
申请号：US13028332
申请日：2011-02-16
IPC分类号： H01L23/62
CPC分类号： H01L23/5258 , H01L23/5254 , H01L23/5256 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.
摘要翻译： 导体填充的损伤传播屏障形成为延伸到保险丝和相邻电路元件之间的低k电介质层，以防止在保险丝熔断操作期间传播损坏。 填充损伤传播屏障的导体材料由与用于形成互连结构的导体层相同的导体层形成。
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