公开(公告)号：US09413055B2

公开(公告)日：2016-08-09

申请号：US14470893

申请日：2014-08-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Alberto Pagani

IPC: H01Q1/00 ,  H01Q1/22 ,  H01L23/48 ,  H01L25/065 ,  H01L23/13 ,  H01L23/66 ,  H01L25/03 ,  H01L25/10 ,  H01L21/56

CPC classification number: H01Q1/2283 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/481 ,  H01L23/66 ,  H01L24/24 ,  H01L25/03 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/73259 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1011 ,  H01L2225/1047 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A base carries a first chip and a second chip oriented differently with respect to the base and packaged in a package. Each chip integrates an antenna and a magnetic via. A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips even if the magnetic path is interrupted, and is formed by a first stretch coupled between the first magnetic-coupling element of the first chip and the first magnetic-coupling element of the second chip, and a second stretch coupled between the second magnetic-coupling element of the first chip and the second magnetic-coupling element of the second chip. The first stretch has a parallel portion extending parallel to the faces of the base. The first and second stretches have respective transverse portions extending on the main surfaces of the second chip, transverse to the parallel portion.

Abstract translation: 基座承载相对于基座不同定向并封装在封装中的第一芯片和第二芯片。 每个芯片集成天线和磁通孔。 磁耦合路径连接芯片，形成磁路，即使磁路中断也能够在芯片之间传递信号和功率，并且由第一芯片和第一芯片之间的第一磁耦合元件形成， 第二芯片的第一磁耦合元件和耦合在第一芯片的第二磁耦合元件和第二芯片的第二磁耦合元件之间的第二延伸部。 第一拉伸具有平行于基部的面延伸的平行部分。 第一和第二延伸部具有横向于平行部分的在第二芯片的主表面上延伸的各自的横向部分。

公开(公告)号：US09257499B2

公开(公告)日：2016-02-09

申请号：US13914820

申请日：2013-06-11

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani

IPC: H01L23/64 ,  H01L27/06 ,  H01L29/94 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L28/90 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment, in a single structure, combines a pad including a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits outside of the chip itself and at least one capacitor. By combining a connection pad and a capacitor in a single structure, it may be possible to reduce the overall area of the chip that otherwise in common integrated circuits would be greater due to the presence of the capacitor itself. In this way, the costs and size of the chip can be reduced.

Abstract translation: 在单个结构中的一个实施例组合了包括适于将集成在芯片中的电路元件与芯片本身外部的电路和至少一个电容器耦合的连接端子的焊盘。 通过以单一结构组合连接焊盘和电容器，由于电容器本身的存在，可以减小芯片的总面积，否则在共同的集成电路中将会更大。 以这种方式，可以降低芯片的成本和尺寸。

公开(公告)号：US09202951B2

公开(公告)日：2015-12-01

申请号：US13933858

申请日：2013-07-02

Applicant: STMicroelectronics S.r.l

Inventor： Alberto Pagani ,  Alessandro Motta ,  Sara Loi

IPC: H01L31/12 ,  H01L31/0232 ,  G02B6/43 ,  G02B6/12 ,  H01L31/103

CPC classification number: H01L31/02327 ,  G02B6/12002 ,  G02B6/12004 ,  G02B6/43 ,  H01L31/103 ,  H01L31/125

Abstract: An integrated electronic device, delimited by a first surface and by a second surface and including: a body made of semiconductor material, formed inside which is at least one optoelectronic component chosen between a detector and an emitter; and an optical path which is at least in part of a guided type and extends between the first surface and the second surface, the optical path traversing the body. The optoelectronic component is optically coupled, through the optical path, to a first portion of free space and a second portion of free space, which are arranged, respectively, above and underneath the first and second surfaces.

Abstract translation: 一种集成的电子器件，由第一表面和第二表面限定，并包括：由半导体材料制成的主体，其内部是在检测器和发射极之间选择的至少一个光电元件; 以及光路，其至少部分地被引导并且在所述第一表面和所述第二表面之间延伸，所述光路穿过所述主体。 光电子部件通过光路被光耦合到自由空间的第一部分和自由空间的第二部分，其分别布置在第一和第二表面的上方和下方。

公开(公告)号：US09076883B2

公开(公告)日：2015-07-07

申请号：US14079976

申请日：2013-11-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Alberto Pagani ,  Giovanni Girlando

IPC: H01L29/82 ,  H01L23/48 ,  H01L23/64 ,  H01L23/66 ,  H01L25/065 ,  H01L25/10 ,  H01Q1/22 ,  H01Q1/36 ,  H01Q7/00 ,  H01L23/00 ,  H01L25/16

CPC classification number: H01L25/0657 ,  G01R1/07314 ,  G01R31/3025 ,  H01L23/48 ,  H01L23/481 ,  H01L23/5227 ,  H01L23/645 ,  H01L23/66 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L28/10 ,  H01L29/82 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/29199 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/29399 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01059 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19042 ,  H01L2924/207 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01Q1/36 ,  H01Q1/38 ,  H01Q7/00 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05552

Abstract: An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna.

Abstract translation: 具有至少部分由半导体材料制成且具有顶表面，底表面和侧表面的主体的集成电子设备的实施例和集成在主体中并且能够进行磁耦合或电磁耦合的第一天线 具有另外的天线的集成电子设备。 集成电子设备还具有由磁性材料制成的耦合区域，其在使用中提供第一天线和另外的天线之间的通信信道。

公开(公告)号：US08976010B2

公开(公告)日：2015-03-10

申请号：US13763707

申请日：2013-02-10

Applicant: STMicroelectronics S.R.L.

Inventor： Alberto Pagani ,  Giovanni Girlando

IPC: G06K7/00 ,  G06K7/10 ,  G06K19/02 ,  G06K19/07 ,  G06K19/073 ,  G06K19/077

CPC classification number: G06K7/00 ,  G06K7/10178 ,  G06K19/025 ,  G06K19/072 ,  G06K19/07327 ,  G06K19/07336 ,  G06K19/07735 ,  G06K19/07756 ,  G06K19/07771 ,  G06K19/07775 ,  G06K19/07779

Abstract: A security system includes an integrated circuit and a transceiver/transponder circuit. The integrated circuit includes an antenna for communicating with the transceiver/transponder circuit. An inhibiting element is associated with the integrated circuit for inhibiting communications with the transceiver/transponder circuit and for securing the data contained in the integrated circuit. The inhibiting element is an electromagnetic inhibiting element. The security system further includes a coupling element associated with the antenna of the integrated circuit for temporarily deactivating the electromagnetic inhibiting element to allow communications between the integrated circuit and the transceiver/transponder circuit.

Abstract translation: 安全系统包括集成电路和收发器/应答器电路。 集成电路包括用于与收发器/应答器电路进行通信的天线。 禁止元件与用于禁止与收发器/应答器电路的通信并用于保护集成电路中包含的数据的集成电路相关联。 抑制元件是电磁抑制元件。 安全系统还包括与集成电路的天线相关联的耦合元件，用于暂时停用电磁抑制元件以允许集成电路和收发器/应答器电路之间的通信。

公开(公告)号：US20140368394A1

公开(公告)日：2014-12-18

申请号：US14470893

申请日：2014-08-27

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Alberto Pagani

IPC: H01Q1/22 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01Q1/2283 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/481 ,  H01L23/66 ,  H01L24/24 ,  H01L25/03 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/73259 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1011 ,  H01L2225/1047 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A base carries a first chip and a second chip oriented differently with respect to the base and packaged in a package. Each chip integrates an antenna and a magnetic via. A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips even if the magnetic path is interrupted, and is formed by a first stretch coupled between the first magnetic-coupling element of the first chip and the first magnetic-coupling element of the second chip, and a second stretch coupled between the second magnetic-coupling element of the first chip and the second magnetic-coupling element of the second chip. The first stretch has a parallel portion extending parallel to the faces of the base. The first and second stretches have respective transverse portions extending on the main surfaces of the second chip, transverse to the parallel portion.

Abstract translation: 基座承载相对于基座不同定向并封装在封装中的第一芯片和第二芯片。 每个芯片集成天线和磁通孔。 磁耦合路径连接芯片，形成磁路，即使磁路被中断也能够在芯片之间传递信号和功率，并且由第一芯片与第一芯片的第一磁耦合元件和 第二芯片的第一磁耦合元件和耦合在第一芯片的第二磁耦合元件和第二芯片的第二磁耦合元件之间的第二延伸部。 第一拉伸具有平行于基部的面延伸的平行部分。 第一和第二延伸部具有横向于平行部分的在第二芯片的主表面上延伸的各自的横向部分。

公开(公告)号：US11808650B2

公开(公告)日：2023-11-07

申请号：US17063147

申请日：2020-10-05

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani ,  Federico Giovanni Ziglioli ,  Bruno Murari

IPC: G01L5/00 ,  G01L1/18 ,  G01L1/20 ,  F16B31/02 ,  G01L5/24

CPC classification number: G01L5/0038 ,  F16B31/028 ,  G01L1/18 ,  G01L1/20 ,  G01L5/243

Abstract: A pressure sensing device may include a body configured to distribute a load applied between first and second parts positioned one against the other, and a pressure sensor carried by the body. The pressure sensor may include a support body, and an IC die mounted with the support body and defining a cavity. The IC die may include pressure sensing circuitry responsive to bending associated with the cavity, and an IC interface coupled to the pressure sensing circuitry.

公开(公告)号：US10985269B2

公开(公告)日：2021-04-20

申请号：US16376468

申请日：2019-04-05

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Paolo Bramanti ,  Alberto Pagani

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H03K17/687 ,  H01L29/205 ,  H01L29/20 ,  H01L21/02 ,  H01L27/06

Abstract: Embodiments are directed to two-dimensional electron gas (2DEG)-confined 2DEG devices and methods. One such device includes a substrate and a heterostructure on the substrate. The heterostructure includes a first semiconductor layer, a second semiconductor layer, and a 2DEG layer between the first and second semiconductor layers. The device further includes a 2DEG device having a conduction channel in the 2DEG layer. An isolation electrode overlies the heterostructure and at least partially surrounds a periphery of the 2DEG device. The isolation electrode, in use, interrupts the 2DEG layer in response to an applied voltage.

公开(公告)号：US10964646B2

公开(公告)日：2021-03-30

申请号：US15854456

申请日：2017-12-26

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani ,  Giovanni Girlando ,  Federico Giovanni Ziglioli ,  Alessandro Finocchiaro

IPC: H01L23/00 ,  G01R31/28 ,  H01L21/762 ,  H01L23/58 ,  H01L21/66 ,  H02J50/20

Abstract: A method of making an integrated circuit (IC) includes forming circuitry over a top surface of a semiconductor substrate having the top surface and an opposite bottom surface. An antenna is formed in an interconnect layer formed above the semiconductor substrate, where the antenna is coupled to circuitry. A seal ring is formed around a periphery of the interconnect layer. The seal ring is disposed around the antenna and the circuitry. A trench with a solid-state insulating material is formed. The trench extends vertically into the semiconductor substrate and extends laterally across the IC.

公开(公告)号：US20210018389A1

公开(公告)日：2021-01-21

申请号：US17063147

申请日：2020-10-05

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani ,  Federico Giovanni Ziglioli ,  Bruno Murari

IPC: G01L5/00 ,  G01L1/18 ,  G01L1/20 ,  F16B31/02

Abstract: A pressure sensing device may include a body configured to distribute a load applied between first and second parts positioned one against the other, and a pressure sensor carried by the body. The pressure sensor may include a support body, and an IC die mounted with the support body and defining a cavity. The IC die may include pressure sensing circuitry responsive to bending associated with the cavity, and an IC interface coupled to the pressure sensing circuitry.