公开(公告)号：US4970106A

公开(公告)日：1990-11-13

申请号：US501073

申请日：1990-03-28

申请人： Thomas H. DiStefano ,  Scott G. Ehrenberg

发明人： Thomas H. DiStefano ,  Scott G. Ehrenberg

IPC分类号： H01L21/48 ,  H05K1/03 ,  H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46

CPC分类号： H01L21/4857 ,  H05K3/4605 ,  H05K1/0306 ,  H05K2201/0154 ,  H05K2201/09318 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/061 ,  H05K2203/1581 ,  H05K3/0041 ,  H05K3/386 ,  H05K3/4061 ,  H05K3/4076 ,  H05K3/4652 ,  Y10S428/901 ,  Y10T428/24917

摘要： A method of assembling a multilayer laminate interconnection board, particularly boards in which each layer preferably includes copper conductors on polyimide film layers, involves adhesively joining individual layers of wired film initially onto an auxiliary pin carrier substrate and then onto a previously laminated layer. After each layer is aligned and adhesively joined to the immediately preceeding layer, holes are formed through the layer. Metal is deposited into the holes for electrically connecting conductors on the top surface of the last layer to a via located on the immediately preceeding layer. The process is repeated for each layer of the multilayer laminate interconnection board until the entire board is completely assembled. Alternatively, layers containing preformed and metalized holes at the location of a respective via in a particular layer are aligned and adhesively laminated.

摘要翻译： 特别是组合多层叠层互连板的方法，特别是其中各层优选地包括聚酰亚胺膜层上的铜导体的板，其中包括将各层有线膜首先粘合到辅助引脚载体衬底上，然后到预先层合的层上。 在每层对准并粘合到紧邻上层之后，通过该层形成孔。 金属沉积在孔中，用于将最后层的顶表面上的导体电连接到位于紧邻上层的通孔。 对于多层叠层互连板的每层重复该过程，直到整个板完全组装为止。 或者，在特定层中的相应通孔的位置处包含预成型和金属化孔的层被对准并粘合层压。

公开(公告)号：US4684547A

公开(公告)日：1987-08-04

申请号：US814349

申请日：1985-12-27

申请人： Thomas H. DiStefano ,  Ralph L. Hollis, Jr. ,  Mark Johnson ,  Sherman S. Wang

发明人： Thomas H. DiStefano ,  Ralph L. Hollis, Jr. ,  Mark Johnson ,  Sherman S. Wang

IPC分类号： G11B23/30 ,  G11B5/58 ,  G11B5/596 ,  G11B5/74 ,  G11B5/82 ,  G11B5/84 ,  G11B23/36 ,  H01F10/00

CPC分类号： B82Y10/00 ,  G11B5/58 ,  G11B5/74 ,  G11B5/743 ,  G11B5/82 ,  G11B5/84 ,  Y10S428/90 ,  Y10S428/928

摘要： A method and apparatus for format patterning magnetic recording media with servo-control patterns is disclosed herein. The method comprises the steps of printing the control pattern using a resist in liquid form onto the media material by conventional printing techniques. A layer of a thin metallic film is then deposited over the resist and uncovered substrate areas. The resist and its overlayered metal is then removed using a liftoff technique by dissolving the resist in its particular solvent. A control pattern of deposited metallic film remains in those non-resist areas. In the alternative, the process can also use an etching bath to create the servo control pattern.

摘要翻译： 本文公开了一种用伺服控制图案形成图案化磁记录介质的方法和装置。 该方法包括以下步骤：使用液体形式的抗蚀剂通过常规印刷技术将控制图案印刷到介质材料上。 然后将一层薄的金属膜沉积在抗蚀剂和未覆盖的基底区域上。 然后使用剥离技术将抗蚀剂及其覆盖的金属溶解在其特定溶剂中。 沉积的金属膜的控制图案保留在那些非抗蚀剂区域中。 在替代方案中，该方法还可以使用蚀刻浴来产生伺服控制图案。

公开(公告)号：US4633451A

公开(公告)日：1986-12-30

申请号：US686634

申请日：1985-01-02

申请人： Kie Y. Ahn ,  Thomas H. DiStefano

发明人： Kie Y. Ahn ,  Thomas H. DiStefano

IPC分类号： G11B5/596 ,  G11B5/82 ,  G11B13/04 ,  G11B5/58 ,  G11B7/08 ,  G11B11/10

CPC分类号： G11B5/59677 ,  G11B5/82

摘要： The surface of a magnetic recording disk is encoded with optically sensed indicia, which is employed to control track following of the read/write slider head along a track on a magnetic recording medium such as a disk. The means of reading the medium is to employ a laser carried by the slider which cooperates with the medium as a reflector which affects the lasing function or modulates the operating characteristics of the laser diode. The retro-reflected light changes the operating voltage of the diode. Preferably, the disk is coated with a multiple layer optical recording medium deposited upon the upper surface of the magnetic recording medium.

摘要翻译： 磁记录盘的表面用光学检测标记编码，其被用于沿磁盘等磁性记录介质上的磁道控制读/写滑块头的跟踪。 读取介质的方法是使用由该滑块携带的激光器，该激光器与介质配合作为影响激光器功能或调制激光二极管的工作特性的反射器。 后反射光改变二极管的工作电压。 优选地，盘被沉积在磁记录介质的上表面上的多层光学记录介质涂覆。

公开(公告)号：US4155785A

公开(公告)日：1979-05-22

申请号：US856941

申请日：1977-12-02

申请人： Jerome J. Cuomo ,  Thomas H. DiStefano ,  Robert Rosenberg

发明人： Jerome J. Cuomo ,  Thomas H. DiStefano ,  Robert Rosenberg

IPC分类号： H01L31/04 ,  H01L31/0368 ,  H01L31/068 ,  H01L31/07 ,  H01L21/22

CPC分类号： H01L31/0368 ,  H01L31/03682 ,  H01L31/068 ,  H01L31/07 ,  Y02E10/546 ,  Y02E10/547 ,  Y10S148/128 ,  Y10S438/922

摘要： The practice of this disclosure obtains a relatively high efficiency operation for a crystalline semiconductor solar cell containing various defects of the linear and planar types. Linear defects include screw dislocations as well as full and partial dislocations. Planar defects include twins, stacking faults, grain boundaries and surfaces. Such defects normally contain recombination centers at which electrons and holes generated in the semiconductor region recombine with loss to the external current of the charge carried thereby. Through application of the principles of this invention, especial dopant concentrations and conductivity regions are established in a finite region around the linear and planar defects so that electrons and holes which are generated in the semiconductor region by incident radiation are substantially collected for external current as consequence thereof.

摘要翻译： 本公开的实践获得了包含线性和平面类型的各种缺陷的晶体半导体太阳能电池的相对高效率的操作。 线性缺陷包括螺旋位错以及全部和部分位错。 平面缺陷包括双胞胎，堆垛层错，晶界和表面。 这样的缺陷通常包含复合中心，在半导体区域中产生的电子和空穴与由此携带的电荷的外部电流的损耗重新组合。 通过应用本发明的原理，在围绕线性和平面缺陷的有限区域内建立了特殊的掺杂剂浓度和导电性区域，使得通过入射辐射在半导体区域中产生的电子和空穴基本上被收集用于外部电流 其中。

公开(公告)号：USRE43404E1

公开(公告)日：2012-05-22

申请号：US12728630

申请日：2010-03-22

申请人： Thomas H. DiStefano ,  Joseph Fjelstad

发明人： Thomas H. DiStefano ,  Joseph Fjelstad

IPC分类号： H01L21/44

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49572 ,  H01L24/32 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80203 ,  H01L2224/80207 ,  H01L2224/81192 ,  H01L2224/81904 ,  H01L2224/83209 ,  H01L2224/9212 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/80001 ,  H01L2224/81

摘要： A method of providing a substantially void free layer for one or more flip chip assemblies, or one or more microelectronic components, utilizing a curable encapsulant. Also disclosed is a method of injecting an encapsulant into an assembly and a method of treating a microelectronic component to form a void free layer.

摘要翻译： 一种利用可固化密封剂为一个或多个倒装芯片组件或一个或多个微电子部件提供基本无空隙的方法。 还公开了将密封剂注入到组件中的方法以及处理微电子部件以形成无空隙层的方法。

公开(公告)号：US07078819B2

公开(公告)日：2006-07-18

申请号：US09854269

申请日：2001-05-11

申请人： Thomas H. DiStefano

发明人： Thomas H. DiStefano

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49805 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/742 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/1184 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/274 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/18301 ,  H05K3/3436 ,  H05K3/363 ,  H05K2201/0215 ,  H05K2201/0248 ,  H05K2201/09427 ,  H05K2201/10977 ,  H05K2203/0465 ,  H05K2203/074 ,  H05K2203/306 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： A soldered assembly for a microelectronic element includes a microelectronic element, solder columns extending from a surface of the microelectronic element and terminals connected to distal ends of the columns. The assembly can be handled and mounted using conventional surface-mount techniques, but provides thermal fatigue resistance. The solder columns may be inclined relative to the chip surface, and may contain long, columnar inclusions preferentially oriented along the lengthwise axes of the columns.

摘要翻译： 用于微电子元件的焊接组件包括微电子元件，从微电子元件的表面延伸的焊料柱和连接到柱的远端的端子。 组件可以使用传统的表面贴装技术进行处理和安装，但提供耐热疲劳性能。 焊料柱可以相对于芯片表面倾斜，并且可以包含沿着柱的纵向轴线优先取向的长的柱状夹杂物。

公开(公告)号：US06541874B2

公开(公告)日：2003-04-01

申请号：US09875383

申请日：2001-06-06

申请人： Tan Nguyen ,  Craig S. Mitchell ,  Thomas H. DiStefano

发明人： Tan Nguyen ,  Craig S. Mitchell ,  Thomas H. DiStefano

IPC分类号： H01L2334

CPC分类号： H01L21/565 ,  H01L21/56 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00

摘要： Microelectronic assemblies are encapsulated using disposable frames. The microelectronic assemblies are disposed within an aperture defined by a frame. The aperture is covered by top and bottom sealing layers so that the frame and sealing layers define an enclosed space encompassing the assemblies. The encapsulant is injected into this closed space. The frame is then separated from the encapsulation fixture and held in a curing oven. After cure, the frame is cut apart and the individual assemblies are severed from one another. Because the frame need not be held in the encapsulation fixture during curing, the process achieves a high throughput.

摘要翻译： 微电子组件使用一次性框架进行封装。 微电子组件设置在由框架限定的孔内。 孔被顶部和底部密封层覆盖，使得框架和密封层限定包围组件的封闭空间。 将密封剂注入该封闭空间。 然后将框架与封装固定装置分离并固定在固化炉中。 固化后，将框架切开，并将各个组件彼此切断。 因为在固化期间框架不需要保持在封装固定件中，所以该工艺实现了高的生产量。

公开(公告)号：US06465747B2

公开(公告)日：2002-10-15

申请号：US09951046

申请日：2001-09-13

申请人： Thomas H. DiStefano ,  Joseph Fjelstad

发明人： Thomas H. DiStefano ,  Joseph Fjelstad

IPC分类号： H01R909

CPC分类号： H01L24/81 ,  H01L23/49838 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/19043 ,  H05K1/111 ,  H05K3/3452 ,  H05K2201/0397 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10734 ,  H05K2201/2081 ,  H05K2203/041 ,  Y02P70/611 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49144

摘要： A microelectronic assembly includes a component having one or more conductive pads, with each conductive pad having a plurality of solder-wettable strips extending outwardly away from a center, the solder wettable strips being bounded by non solder-wettable material. The microelectronic assembly also includes a composite conductive element positioned atop at least one of the conductive pads, the composite conductive element including a solid conductive core and a layer of solder material overlying the solid conductive core, the solid conductive core having a higher melting temperature than the layer of solder material.

摘要翻译： 微电子组件包括具有一个或多个导电焊盘的部件，每个导电焊盘具有从中心向外延伸的多个可焊接润湿的条，焊料可润湿条由非焊料可润湿材料限定。 微电子组件还包括位于至少一个导电焊盘顶部的复合导电元件，复合导电元件包括​​固体导电芯和覆盖在固体导电芯上的焊料层，该固体导电芯的熔化温度高于 该焊料层。

公开(公告)号：US06335222B1

公开(公告)日：2002-01-01

申请号：US09157047

申请日：1998-09-18

申请人： Thomas H. DiStefano

发明人： Thomas H. DiStefano

IPC分类号： H01L2144

CPC分类号： H01L24/81 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49805 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/742 ,  H01L24/94 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/1184 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/274 ,  H01L2224/29101 ,  H01L2224/29298 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/18301 ,  H05K3/3436 ,  H05K3/363 ,  H05K2201/0215 ,  H05K2201/0248 ,  H05K2201/09427 ,  H05K2201/10977 ,  H05K2203/0465 ,  H05K2203/074 ,  H05K2203/306 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

摘要： A soldered assembly such as a packaged semiconductor chip includes elongated solder columns connected to the pads on the chip and a dielectric sheet having pads connected to the distal ends of the solder columns remote from the chip. Terminals on the sheet are connected to the pads of the sheet. The assembly can be handled and mounted using conventional surface-mount techniques, but provides thermal fatigue resistance. The solder columns may be inclined relative to the chip surface, and may contain long, columnar inclusions preferentially oriented along the lengthwise axes of the columns.

摘要翻译： 诸如封装半导体芯片的焊接组件包括连接到芯片上的焊盘的细长焊料柱和具有连接到远离芯片的焊料柱的远端的焊盘的电介质片。 纸张上的端子连接到纸张的垫。 组件可以使用传统的表面贴装技术进行处理和安装，但提供耐热疲劳性能。 焊料柱可以相对于芯片表面倾斜，并且可以包含沿着柱的纵向轴线优先取向的长的柱状夹杂物。

公开(公告)号：US06272744B1

公开(公告)日：2001-08-14

申请号：US09317648

申请日：1999-05-24

申请人： Thomas H. DiStefano ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaètan Mathiew

发明人： Thomas H. DiStefano ,  Gary W. Grube ,  Igor Y. Khandros ,  Gaètan Mathiew

IPC分类号： H05K330

CPC分类号： H01L23/49838 ,  H01L23/3107 ,  H01L23/4985 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/01082 ,  H05K3/361 ,  H05K3/4084 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49151 ,  H01L2924/00

摘要： A connection component for electrically connecting a semiconductor chip to a support substrate incorporates a preferably dielectric supporting structure defining gaps. Leads extend across these gaps so that the leads are supported on both sides of the gap. The leads therefore can be positioned approximately in registration to contacts on the chip by aligning the connection component with the chip. Each lead is arranged so that one end can be displaced relative to the supporting structure when a downward force is applied to the lead. This allows the leads to be connected to the contacts on the chip by engaging each lead with a tool and forcing the lead downwardly against the contact. Preferably, each lead incorporates a frangible section adjacent one side of the gap and the frangible section is broken when the lead is engaged with the contact. Final alignment of the leads with the contacts on the chip is provided by the bonding tool, which has features adapted to control the position of the lead.

摘要翻译： 用于将半导体芯片电连接到支撑衬底的连接部件包含限定间隙的优选介电支撑结构。 引线延伸穿过这些间隙，使得引线支撑在间隙的两侧。 因此，引线可以通过将连接部件与芯片对准而大致对准芯片上的触点。 每个引线被布置成使得当向引线施加向下的力时，一端可相对于支撑结构移位。 这允许引线通过使每个引线与工具接合并将引线向下抵靠接触件而连接到芯片上的触点。 优选地，每个引线包括与间隙的一侧相邻的易碎部分，并且当引线与触点接合时，易碎部分断裂。 引线与芯片上的触点的最终对准由焊接工具提供，其具有适于控制引线位置的特征。