公开(公告)号：US07482259B2

公开(公告)日：2009-01-27

申请号：US12025000

申请日：2008-02-02

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

IPC分类号： H01L21/44 ,  H01L23/04

CPC分类号： H01L23/5283 ,  H01L23/5286 ,  H01L23/5329 ,  H01L24/02 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L27/0248 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00

摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

公开(公告)号：US20090008778A1

公开(公告)日：2009-01-08

申请号：US12206751

申请日：2008-09-09

申请人： Jin-Yuan Lee ,  Ching-Cheng Huang ,  Mou-Shiung Lin

发明人： Jin-Yuan Lee ,  Ching-Cheng Huang ,  Mou-Shiung Lin

IPC分类号： H01L23/48

CPC分类号： H01L23/293 ,  H01L23/3114 ,  H01L23/49827 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

公开(公告)号：US07345365B2

公开(公告)日：2008-03-18

申请号：US10728150

申请日：2003-12-03

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L23/40 ,  H01L23/34 ,  H01L23/538

CPC分类号： H01L21/6835 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  Y10T29/5313 ,  Y10T29/5317 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

摘要： An integrated chip package structure and method of manufacturing the same is by adhering dies on an organic substrate and forming a thin-film circuit layer on top of the dies and the organic substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

摘要翻译： 集成芯片封装结构及其制造方法是通过在有机基板上附着模具并在模具和有机基板的顶部形成薄膜电路层。 其中薄膜电路层具有电连接到模具的金属焊盘的外部电路，其延伸到模具的有效表面外部的区域，以扇出模具的金属焊盘。 此外，多个有源器件和内部电路位于管芯的有效表面上。 有源器件的信号通过内部电路传输到外部电路，并通过内部电路从外部电路传输回其他有源器件。 此外，芯片封装结构允许将具有不同功能的多个裸片封装在集成封装中并通过外部电路电连接裸片。

公开(公告)号：US07309920B2

公开(公告)日：2007-12-18

申请号：US11123936

申请日：2005-05-06

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L28/10 ,  H01L21/768 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/60 ,  H01L24/02 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L27/0251 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/20 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04953 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10T29/49124 ,  Y10T29/49204 ,  H01L2924/00

摘要： A chip or wafer comprises a semiconductor substrate, first and second transistors on the semiconductor substrate, first and second metal layers over the semiconductor substrate, an insulating layer on the first and second metal layers, a third and fourth metal layers on the insulating layer, a passivation layer over the third and fourth metal layers, and a fifth metal layer over the passivation layer. A signal is suited to be transmitted from the first transistor to the second transistor sequentially through the first, third, fifth, fourth and second metal layers.

摘要翻译： 芯片或晶片包括半导体衬底，半导体衬底上的第一和第二晶体管，半导体衬底上的第一和第二金属层，第一和第二金属层上的绝缘层，绝缘层上的第三和第四金属层， 在第三和第四金属层上的钝化层，以及钝化层上的第五金属层。 信号适合于通过第一，第三，第五，第四和第二金属层从第一晶体管顺序地传输到第二晶体管。

公开(公告)号：US20050090099A1

公开(公告)日：2005-04-28

申请号：US10996537

申请日：2004-11-24

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

IPC分类号： H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/538 ,  H01L21/4763

CPC分类号： H01L24/19 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/5389 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/83

摘要： A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

摘要翻译： 使用用于金属互连结构的绝缘层的低介电常数（k）聚合物材料来提供薄膜半导体管芯电路封装。 五个实施方案包括利用玻璃，玻璃 - 金属复合材料和玻璃/玻璃夹层基材。 基板形成用于安装半导体管芯的基座并制造薄膜互连结构。

公开(公告)号：US20050032351A1

公开(公告)日：2005-02-10

申请号：US10933961

申请日：2004-09-02

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee ,  Ching-Cheng Huang

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/60 ,  H01L27/06 ,  H01L27/08 ,  H01L21/4763

CPC分类号： H01L28/10 ,  H01L21/768 ,  H01L21/76807 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/5329 ,  H01L23/60 ,  H01L27/0676 ,  H01L27/08 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/15174 ,  H01L2924/00

摘要： A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer. The second built-up layer is provided with a second dielectric body and a second interconnection scheme, wherein the second interconnection scheme interlaces inside the second dielectric body and is electrically connected to the first interconnection scheme. The second interconnection scheme is constructed from at least one second metal layer and at least one via metal filler, wherein the second metal layer is electrically connected to the via metal filler. The thickness, width, and cross-sectional area of the traces of the second metal layer are respectively larger than those of the first metal layers.

公开(公告)号：US20050032349A1

公开(公告)日：2005-02-10

申请号：US10935451

申请日：2004-09-07

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

IPC分类号： H01L21/60 ,  H01L21/98 ,  H01L23/485 ,  H01L25/065 ,  H01L21/48 ,  H01L21/44 ,  H01L21/50 ,  H01L47/00

CPC分类号： H01L24/12 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13007 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00

摘要： A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

摘要翻译： 阻挡层沉积在包括在钝化层中形成的接触垫的开口中的钝化层上。 形成三层金属层，覆盖在阻挡层上并与接触焊盘对齐并具有大约等于接触焊盘表面的直径。 当从与阻挡层接触的层进行时，柱的三个金属层依次包括一层柱状金属，一块下凸块金属和一层焊料金属。 柱金属层的直径减小，阻挡层从钝化层的表面选择性地去除，之后焊料金属的回流完成了本发明的焊料凸块。

公开(公告)号：US06818545B2

公开(公告)日：2004-11-16

申请号：US09798654

申请日：2001-03-05

申请人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

发明人： Jin-Yuan Lee ,  Mou-Shiung Lin ,  Ching-Cheng Huang

IPC分类号： H01L2144

CPC分类号： H01L24/12 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13007 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00

摘要： A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

摘要翻译： 阻挡层沉积在包括在钝化层中形成的接触垫的开口中的钝化层上。 形成三层金属层，覆盖在阻挡层上并与接触焊盘对齐并具有大约等于接触焊盘表面的直径。 当从与阻挡层接触的层进行时，柱的三个金属层依次包括一层柱状金属，一块下凸块金属和一层焊料金属。 柱金属层的直径减小，阻挡层从钝化层的表面选择性地去除，之后焊料金属的回流完成了本发明的焊料凸块。

公开(公告)号：US06495912B1

公开(公告)日：2002-12-17

申请号：US09953610

申请日：2001-09-17

申请人： Ching-Cheng Huang ,  Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Ching-Cheng Huang ,  Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23053

CPC分类号： H01L23/49822 ,  H01L21/4857 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K1/0306 ,  H05K1/16 ,  H05K3/4605 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A new method and structure is provided to create a System On Package (SOP). The process starts with a ceramic substrate that is typically used as the basis for a ceramic substrate. One or more layers of dielectric such as polyimide are deposited over the surface of the ceramic substrate, patterned and etched to created openings in the one or more layers of dielectric that align with conductive plugs that have been provided in the ceramic substrate. Passive components and metal interconnections can be created on the surface of the layers of dielectric using thin film technology. As a final step, a protective layer of dielectric is deposited over the surface of the top layer of dielectric. Active semiconductor devices may be attached to the surface of the SOP, heat sinks can be attached to the semiconductor devices. The SOP may further be mounted on the surface of a Printed Circuit Board.

摘要翻译： 提供了一种新的方法和结构来创建一个系统包（SOP）。 该方法从通常用作陶瓷衬底的基础的陶瓷衬底开始。 一层或多层电介质如聚酰亚胺沉积在陶瓷衬底的表面上，被图案化和蚀刻，以在与陶瓷衬底中提供的导电插塞对准的一个或多个电介质层中形成开口。 可以使用薄膜技术在电介质层的表面上形成被动元件和金属互连。 作为最后的步骤，电介质的保护层沉积在电介质顶层的表面上。 有源半导体器件可以附着在SOP的表面上，散热器可以附着到半导体器件上。 SOP还可以安装在印刷电路板的表面上。

公开(公告)号：US09142527B2

公开(公告)日：2015-09-22

申请号：US11926156

申请日：2007-10-29

申请人： Jin-Yuan Lee ,  Ying-Chih Chen ,  Mou-Shiung Lin

发明人： Jin-Yuan Lee ,  Ying-Chih Chen ,  Mou-Shiung Lin

IPC分类号： H01L21/4763 ,  H01L23/00

CPC分类号： H01L24/48 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/854 ,  H01L2224/85424 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/04953 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.