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1.
公开(公告)号:US08742580B2
公开(公告)日:2014-06-03
申请号:US11678600
申请日:2007-02-25
申请人: Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
发明人: Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
IPC分类号: H01L23/48
CPC分类号: H01L24/48 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05187 , H01L2224/05548 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/45144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/854 , H01L2224/85424 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/04953 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
摘要翻译: 提供了一种方法和结构,以在集成电路管芯上形成的有源和/或无源器件和/或低k电介质上实现引线接合连接。 提供了具有有源和/或无源器件的半导体衬底,其中在有源和/或无源器件上形成互连金属化。 提供了形成在互连金属化之上的钝化层,其中在钝化层中形成开口以形成互连金属化的上金属层。 柔性金属焊盘形成在钝化层上方,其中柔性金属接合焊盘通过开口连接到上金属层,并且其中柔性金属接合焊盘基本上形成在有源和/或无源器件的上方。 顺应性金属接合焊盘可以由复合金属结构形成。
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公开(公告)号:US08426958B2
公开(公告)日:2013-04-23
申请号:US13159368
申请日:2011-06-13
IPC分类号: H01L23/02
CPC分类号: H01L25/0657 , H01L23/3128 , H01L23/525 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/06135 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/4824 , H01L2224/49 , H01L2224/73215 , H01L2224/73265 , H01L2224/92147 , H01L2224/92247 , H01L2225/0651 , H01L2225/06558 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.
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公开(公告)号:US20110241183A1
公开(公告)日:2011-10-06
申请号:US13159368
申请日:2011-06-13
IPC分类号: H01L23/58 , H01L23/488
CPC分类号: H01L25/0657 , H01L23/3128 , H01L23/525 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/06135 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48227 , H01L2224/4824 , H01L2224/49 , H01L2224/73215 , H01L2224/73265 , H01L2224/92147 , H01L2224/92247 , H01L2225/0651 , H01L2225/06558 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/15788 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要: A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate.
摘要翻译: 芯片封装包括具有第一侧和第二侧的第一芯片,其中所述第一芯片包括第一焊盘,第一焊盘,第二焊盘和在其第一侧的第一钝化层,所述第一钝化层中的开口 暴露所述第一焊盘,所述第一迹线在所述第一钝化层之上,所述第一迹线将所述第一焊盘连接到所述第二焊盘; 具有第一侧和第二侧的第二芯片,其中所述第二芯片包括在其第一侧的第一焊盘,其中所述第二芯片的所述第二侧与所述第二芯片的所述第二侧接合; 与所述第一芯片的所述第一侧或所述第二芯片的所述第一侧连接的衬底; 连接所述第一芯片的所述第二焊盘和所述衬底的第一引线接合线; 以及连接所述第二芯片的所述第一焊盘和所述衬底的第二引线键合线。
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4.
公开(公告)号:US07577321B2
公开(公告)日:2009-08-18
申请号:US11790547
申请日:2007-04-26
申请人: Chien-Chun Lu , Shin-Ge Lee , Chun-Hsing Lee , Shun-Tien Lee , Ying-Chih Chen
发明人: Chien-Chun Lu , Shin-Ge Lee , Chun-Hsing Lee , Shun-Tien Lee , Ying-Chih Chen
IPC分类号: G02B6/12
CPC分类号: G02B6/43 , G02B6/12002 , G02B6/12004 , H05K1/0274 , H05K2201/0959 , H05K2201/2054
摘要: A hybrid electro-optical circuit board including a plate, a light guiding hole and a light-guide device. The light guiding hole is formed in the plate to be connected to an upper surface and a lower surface of the plate. The light-guide device is formed on the lower surface and covers and contacts the light guiding hole. An optical signal is transmitted between the light-guide device and the upper surface of the plate via the light guiding hole. A metal layer is further formed on an inner wall of the light guiding hole, to reduce the roughness of the inner wall and reflects the optical signal by the reflection characteristics of metal. Further, the light guiding hole is filled with a transparent substance to transmit the optical signal and to stop foreign material from entering the light guiding hole.
摘要翻译: 一种混合电光电路板,包括板,导光孔和导光装置。 导光孔形成在板中以连接到板的上表面和下表面。 导光装置形成在下表面上并覆盖并接触导光孔。 光信号经由导光孔在导光装置与板的上表面之间传递。 金属层进一步形成在导光孔的内壁上,以减小内壁的粗糙度,并通过金属的反射特性反射光信号。 此外,导光孔填充有透明物质以透射光信号并阻止异物进入导光孔。
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公开(公告)号:US20060140550A1
公开(公告)日:2006-06-29
申请号:US11074733
申请日:2005-03-09
申请人: Yi-Ming Chen , Ying-Chih Chen , Yao-Ling Cheng , Shun-Tien Lee
发明人: Yi-Ming Chen , Ying-Chih Chen , Yao-Ling Cheng , Shun-Tien Lee
IPC分类号: G02B6/42
CPC分类号: H01L27/14618 , G02B6/4206 , G02B6/425 , H01L25/167 , H01L27/14625 , H01L27/14627 , H01L27/14634 , H01L27/14685 , H01L33/58 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00011 , H01L2924/00014 , H05K1/141 , H05K1/183 , H01L2224/0401
摘要: An array optical sub-assembly includes a base seat, an integrated circuit, a transparent substrate and a photoelectric element. The integrated circuit and the photoelectric element are bonded respectively to the base seat and the transparent substrate. The base seat and the transparent substrate form a sealed space to protect the elements. The photoelectric element and the integrated circuit are separated to avoid thermal interference between the photoelectric element and the integrated circuit. Therefore total performance is increased and fabrication difficulty is reduced.
摘要翻译: 阵列光学子组件包括基座,集成电路,透明基板和光电元件。 集成电路和光电元件分别结合到基座和透明基板。 基座和透明基板形成密封空间以保护元件。 分离光电元件和集成电路,以避免光电元件与集成电路之间的热干扰。 因此,总体性能提高,制造难度降低。
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公开(公告)号:US20050051881A1
公开(公告)日:2005-03-10
申请号:US10933349
申请日:2004-09-03
申请人: Ying-Chih Chen , Yun-Hsiang Tien , Ming-Jiun Lai , Yi-Chuan Ding
发明人: Ying-Chih Chen , Yun-Hsiang Tien , Ming-Jiun Lai , Yi-Chuan Ding
IPC分类号: H01L23/02 , H01L23/495 , H01L23/498 , H01L23/538 , H01L23/544 , H01L23/60 , H05K1/02 , H05K3/00 , H05K3/06 , H05K3/24 , H05K3/28
CPC分类号: H01L24/97 , H01L23/49838 , H01L23/5386 , H01L23/544 , H01L23/60 , H01L2223/54473 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H05K1/0269 , H05K3/0047 , H05K3/0052 , H05K3/06 , H05K3/242 , H05K3/28 , H05K2201/09918 , H05K2203/0574 , H05K2203/175 , H01L2924/00
摘要: The present invention provides a structure and a method for prevention leakage of a substrate strip. The substrate strip includes an edge portion and a plurality of units. A patterned metal layer on a surface of the substrate strip includes at least one plating bus extended to the edge portion, a plurality of plating lines at the units, a plurality of contact pads at the units and a plurality of fiducial marks at the edge portion. The plating bus has an extended trail having one end exposed out of the sidewall of the substrate strip. The fiducial marks and the contact pads are exposed out of a plurality of first openings of a solder mask. The solder mask also has a second opening at the edge portion exposing a portion of the plating bus to define a breaking hole. After forming a surface layer on the fiducial marks and the contact pads, the exposed portion of the plating bus is void of the surface layer. By removing the exposed portion of the plating bus, the breaking hole is formed to electrically isolate the extended trail from the contact pads in order to prevent a chip on the substrate strip from being damaged by ESD (Electrostatic Discharge) during packaging processes.
摘要翻译: 本发明提供了一种用于防止衬底条的泄漏的结构和方法。 衬底条包括边缘部分和多个单元。 衬底条表面上的图案化金属层包括延伸到边缘部分的至少一个电镀母线,在该单元处的多条电镀线,在该单元处的多个接触焊盘和在边缘部分处的多个基准标记 。 电镀母线具有一个伸出的线,其一端暴露在衬底带的侧壁外。 基准标记和接触垫从焊料掩模的多个第一开口露出。 焊接掩模还在边缘部分处具有暴露电镀总线的一部分以限定断裂孔的第二开口。 在基准标记和接触焊盘上形成表面层之后,电镀总线的露出部分没有表面层。 通过去除电镀总线的暴露部分,形成断开孔以将延伸的迹线与接触焊盘电隔离,以防止在封装过程中ESD(静电放电)在衬底条上的芯片被损坏。
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公开(公告)号:US06698984B1
公开(公告)日:2004-03-02
申请号:US10294744
申请日:2002-11-15
申请人: Ying-Chih Chen
发明人: Ying-Chih Chen
IPC分类号: B60P715
CPC分类号: B60P7/15
摘要: An improved structure extendible tip shoring bar comprising an outer rod connected to a base enables the extension and retraction inserted inside the outer rod and base. The base having a levering handle, a safety catch, and an L-shaped linkage, wherein an anterior pawl and a posterior pawl disposed at the front extremity of the levering handle. The posterior pawl and the levering handle are rotatably coupled to the base, while the anterior and posterior pawls contact unidirectionally inclined teeth. Furthermore, a pin projects from the front aspect, with each subjected to tension from the two extremities of an encompassing arcuate spring, and the surface and spring side is against the safety catch and L-shaped linkage. Conversely, toggling the safety catch to actuate the L-shaped linkage and elevate the anterior and the posterior pawls allow the inner rod pushed inside the outer rod, achieving a more convenient operation.
摘要翻译: 一种改进的结构可扩展尖端支杆,其包括连接到基座的外杆,能够将伸出和缩回插入外杆和底座内。 所述基座具有杠杆手柄,安全锁扣和L形连杆,其中前杠杆和后爪设置在杠杆手柄的前端。 后爪和杠杆手柄可旋转地联接到基座,而前爪和后爪接触单向倾斜的齿。 此外,销从前方突出,每个都受到包围的弓形弹簧的两个末端的张力,并且表面和弹簧侧抵靠安全锁扣和L形连杆。 相反,切换安全锁定器以致动L形连杆并提升前爪和后爪允许将内杆推到外杆内部,实现更方便的操作。
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公开(公告)号:US4612645A
公开(公告)日:1986-09-16
申请号:US683776
申请日:1984-12-19
申请人: Jia-Ming Liu , Ying-Chih Chen
发明人: Jia-Ming Liu , Ying-Chih Chen
CPC分类号: H01S5/06209 , H01S5/32 , H01S5/06236 , H01S5/3201 , H01S5/32391
摘要: The laser device of the present invention comprises: a semiconductor substrate; a first cladding layer of semiconductor formed on the substrate; an active layer of semiconductor formed on the first cladding layer, thereby forming a junction plane between the active layer and the first cladding layer; a second cladding layer of semiconductor formed on the active layer and a cap layer of semiconductor formed on the second cladding layer; the active layer having a lattice constant parallel to the junction plane sufficiently larger than the lattice constant normal to the junction plane so as to increase the optical gain of the TM mode relative to the optical gain of the normally operating TE mode, such that at a first injection current level, the laser device operates in the TM mode and at a second injection current level, the laser device operates in the TE mode. The laser output of the laser device of the present invention can be switched between a pure TM mode and a pure TE mode with nanosecond response time by varying injection current levels of the device.
摘要翻译: 本发明的激光装置包括:半导体基板; 形成在所述基板上的第一半导体包层; 形成在所述第一包层上的有源层半导体,从而在所述有源层与所述第一包层之间形成接合面; 形成在有源层上的第二半导体层和形成在第二覆层上的半导体帽层; 所述有源层具有平行于所述结面的晶格常数,其足够大于垂直于所述结面的晶格常数,从而相对于所述正常工作的TE模的光学增益增加所述TM模的光学增益,使得在 第一注入电流水平,激光器件以TM模式工作,并且在第二注入电流水平下操作,激光器件以TE模式工作。 本发明的激光装置的激光输出可以通过改变装置的注入电流水平,在纯TM模式和纯TE模式之间通过纳秒响应时间进行切换。
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公开(公告)号:US09142527B2
公开(公告)日:2015-09-22
申请号:US11926156
申请日:2007-10-29
申请人: Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
发明人: Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
IPC分类号: H01L21/4763 , H01L23/00
CPC分类号: H01L24/48 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05187 , H01L2224/05548 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/45144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/854 , H01L2224/85424 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/04953 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
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10.
公开(公告)号:US07521812B2
公开(公告)日:2009-04-21
申请号:US11678598
申请日:2007-02-25
申请人: Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
发明人: Jin-Yuan Lee , Ying-Chih Chen , Mou-Shiung Lin
IPC分类号: H01L23/485 , H01L23/49
CPC分类号: H01L24/48 , H01L24/03 , H01L24/05 , H01L2224/02166 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05171 , H01L2224/05187 , H01L2224/05548 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05644 , H01L2224/45144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/854 , H01L2224/85424 , H01L2224/85444 , H01L2224/85447 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/04953 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要: A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
摘要翻译: 提供了一种方法和结构,以在集成电路管芯上形成的有源和/或无源器件和/或低k电介质上实现引线接合连接。 提供了具有有源和/或无源器件的半导体衬底,其中在有源和/或无源器件上形成互连金属化。 提供了形成在互连金属化之上的钝化层,其中在钝化层中形成开口以形成互连金属化的上金属层。 柔性金属焊盘形成在钝化层上方,其中柔性金属接合焊盘通过开口连接到上金属层,并且其中柔性金属接合焊盘基本上形成在有源和/或无源器件的上方。 顺应性金属接合焊盘可以由复合金属结构形成。
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