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公开(公告)号：US09443113B2
公开(公告)日：2016-09-13
申请号：US14942665
申请日：2015-11-16
发明人： Syed M. Alam , Thomas Andre
CPC分类号： G06F21/79 , G06F3/062 , G06F3/0653 , G06F3/0679 , G06F21/78 , G06F21/86 , G06F2221/2143 , G11C7/24 , G11C11/1695
摘要： In response to a tamper-attempt indication, a memory device selectively disables one or more memory operations. Disabling can be accomplished by different techniques, including altering bias voltages associated with performing the memory operation, gating off a current needed for performing the memory operation, and limiting the needed current to a magnitude below the threshold magnitude required for the operation. After disabling the memory operation, a mock current can be generated. The mock current is intended to mimic the current normally expended during the memory operation when not disabled, thereby leading a user to believe that the device is continuing to operate normally even though the memory operation that is being attempted is not actually being performed.
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72.发明授权公开(公告)号：US09418001B2
公开(公告)日：2016-08-16
申请号：US14827628
申请日：2015-08-17
发明人： Syed M. Alam , Thomas Andre , Dietmar Gogl
IPC分类号： G11C11/00 , G06F12/02 , G11C7/10 , G11C11/4076 , G11C8/04 , G06F12/06 , G11C11/16 , G11C11/4094 , G11C11/4096 , G11C14/00
CPC分类号： G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0246 , G06F12/0638 , G06F13/1694 , G06F2212/205 , G06F2212/7201 , G11C7/1042 , G11C7/1072 , G11C8/04 , G11C11/005 , G11C11/16 , G11C11/1673 , G11C11/1675 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C14/0036
摘要： A memory system and memory controller for interleaving volatile and non-volatile memory accesses are described. In the memory system, the memory controller is coupled to the volatile and non-volatile memories using a shared address bus. Activate latencies for the volatile and non-volatile memories are different, and registers are included on the memory controller for storing latency values. Additional registers on the memory controller store precharge latencies for the memories as well as page size for the non-volatile memory. A memory access sequencer on the memory controller asserts appropriate chip select signals to the memories to initiate operations therein.
摘要翻译： 描述了用于交织易失性和非易失性存储器访问的存储器系统和存储器控制器。 在存储器系统中，存储器控制器使用共享地址总线耦合到易失性和非易失性存储器。 激活易失性和非易失性存储器的延迟是不同的，寄存器包含在存储器控制器中用于存储延迟值。 存储器控制器上的附加寄存器存储存储器的预充电延迟以及非易失性存储器的页面大小。 存储器控制器上的存储器访问定序器向存储器发出适当的片选信号以启动其中的操作。
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公开(公告)号：US09378792B2
公开(公告)日：2016-06-28
申请号：US13631395
申请日：2012-09-28
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1673 , G11C13/0002 , G11C13/0097
摘要： A method for determining an optimized write pattern for low write error rate operation of a spin torque magnetic random access memory. The method provides a way to optimize the write error rate without affecting the memory speed. The method comprises one or more write pulses. The pulses may be independent in amplitude, duration and shape. Various exemplary embodiments adjust the write pattern based on the memory operating conditions, for example, operating temperature.
摘要翻译： 一种用于确定用于自旋扭矩磁随机存取存储器的低写入错误率操作的优化写入模式的方法。 该方法提供了一种优化写错误率而不影响内存速度的方法。 该方法包括一个或多个写入脉冲。 脉冲在振幅，持续时间和形状上可以是独立的。 各种示例性实施例基于存储器操作条件（例如，工作温度）来调整写入模式。
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公开(公告)号：US20160163962A1
公开(公告)日：2016-06-09
申请号：US15041178
申请日：2016-02-11
发明人： Phillip MATHER , Jon SLAUGHTER , Nicholas RIZZO
IPC分类号： H01L43/02
CPC分类号： H01L43/02 , G01R33/098 , H01L27/22 , H01L43/08 , H01L43/12
摘要： A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout. The X and Y pitch of the sense elements are arranged such that the line segment that stabilizes, for example, the right side of one sense element; also stabilizes the left side of the adjacent sense element.
摘要翻译： 磁传感器包括多个组，每个组包括多个磁隧道结（MTJ）装置，其具有多个导体，其被配置成并联连接一组内的MTJ装置，并且该组可串联实现材料电阻的独立优化 面积（RA），并设置总的器件电阻，使得总的桥接电阻不是很高，以至于Johnson噪声成为限制信号的关键，而不是那么低，使得CMOS元件可能会削弱读取信号。 或者，串联的至少两组中的每一个中的磁隧道结装置和并联的至少两个组，导致电连接路径的单独配置和参考层的磁参考方向，导致两者的独立优化 功能，以及更多设备设计和布局自由。 感测元件的X和Y间距被布置成使得例如稳定一个感测元件的右侧的线段; 也稳定了相邻感测元件的左侧。
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75.发明授权Non-reactive photoresist removal and spacer layer optimization in a magnetoresistive device 有权磁阻器件中的非反应性光致抗蚀剂去除和间隔层优化公开(公告)号：US09343661B2
公开(公告)日：2016-05-17
申请号：US14296189
申请日：2014-06-04
CPC分类号： H01L43/12 , H01L27/222 , H01L43/08
摘要： In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.
摘要翻译： 在形成用于磁阻器件的顶部电极时，使用非反应性剥离工艺剥离用于图案化电极的光致抗蚀剂。 这种非反应性汽提方法使用水蒸汽或一些其它非氧化气体，其也钝化了磁阻装置的暴露部分。 在这种磁阻器件中，包括非反应性间隔层，其有助于防止磁阻器件中的层之间的扩散，其中间隔层的非反应性质防止可能干扰磁阻的下部的精确形成的侧壁粗糙度 设备。
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公开(公告)号：US09336872B2
公开(公告)日：2016-05-10
申请号：US14495678
申请日：2014-09-24
发明人： Thomas Andre
CPC分类号： G11C11/1673 , G06F11/1068 , G09C1/00 , G11C5/06 , G11C11/1659 , G11C11/1675 , G11C13/0002 , G11C13/0026 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C14/0081 , G11C14/009 , G11C29/52 , G11C2213/75 , G11C2213/77 , H01L27/228 , H01L43/02 , H01L43/08 , H04L9/0866
摘要： In some examples, a nonvolatile storage element may be configured to store a state or value during a low power or powered down period of a circuit. For example, the nonvolatile storage element may include a bridge of resistive elements that have a resistive state that may be configured by applying voltages to multiple drive paths. A sense amplifier may be connected to the bridge in order to resolve a voltage differential associated with the bridge to ether power or ground and, thereby determine the state associated with on the nonvolatile storage element.
摘要翻译： 在一些示例中，非易失性存储元件可以被配置为在电路的低功率或掉电时段期间存储状态或值。 例如，非易失性存储元件可以包括具有电阻状态的电阻元件桥，其可以通过向多个驱动路径施加电压来配置。 感测放大器可以连接到桥，以便将与桥接器相关联的电压差分解成以太网电力或接地，从而确定与非易失性存储元件相关联的状态。
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公开(公告)号：US09336848B2
公开(公告)日：2016-05-10
申请号：US14727965
申请日：2015-06-02
CPC分类号： G11C11/1673 , G11C11/1659 , G11C11/1675
摘要： In some examples, a memory device may be configured to utilize differential bit cells formed from two or more tunnel junctions. In some cases, the tunnel junctions forming the differential bit cell may be arranged to utilize shared read circuitry to reduce device mismatch. For instance, the read operations associated with both tunnel junction may be time multiplexed such that the same preamplifier circuitry may sense voltages representative of the tunnel junctions.
摘要翻译： 在一些示例中，存储器件可以被配置为利用由两个或更多个隧道结形成的差分位单元。 在一些情况下，形成差分位单元的隧道结可以被布置为利用共享读取电路来减少器件失配。 例如，与隧道结相关联的读取操作可以被时间复用，使得相同的前置放大器电路可以感测代表隧道结的电压。
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78.发明授权Word line auto-booting in a spin-torque magnetic memory having local source lines 有权字线在具有本地源极线的自旋转矩磁存储器中自动启动公开(公告)号：US09286218B2
公开(公告)日：2016-03-15
申请号：US14495151
申请日：2014-09-24
发明人： Thomas Andre , Syed M. Alam
IPC分类号： G11C7/12 , G11C11/16 , G11C7/08 , G06F12/08 , G11C11/4094 , G11C11/419 , G11C11/4091 , G11C11/56
CPC分类号： G11C11/1675 , G06F12/0806 , G06F12/0879 , G06F2212/62 , G11C7/1018 , G11C7/1045 , G11C7/12 , G11C7/22 , G11C11/16 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C11/4091 , G11C11/4094 , G11C11/419 , G11C11/5607 , Y02D10/13
摘要： In a spin-torque magnetic random access memory (MRAM) that includes local source lines, auto-booting of the word line is used to conserve power consumption by reusing charge already present from driving a plurality of bit lines during writing operations. Auto-booting is accomplished by first driving the word line to a first word line voltage. After such driving, the word line isolated. Subsequent driving of the plurality of bit lines that are capacitively coupled to the word line causes the word line voltage to be increased to a level desired to allow sufficient current to flow through a selected memory cell to write information into the selected memory cell. Additional embodiments include the use of a supplemental voltage provider that is able to further boost or hold the isolated word line at the needed voltage level.
摘要翻译： 在包括本地源线的自旋扭矩磁随机存取存储器（MRAM）中，字线的自动引导用于通过在写入操作期间重新使用已经存在的驱动多个位线的电荷来节省功耗。 通过首先将字线驱动到第一字线电压来实现自动启动。 经过这样的驾驶，字线隔离。 随后驱动电容耦合到字线的多个位线使得字线电压增加到期望的水平，以允许足够的电流流过选定的存储器单元以将信息写入所选存储单元。 另外的实施例包括使用能够进一步升高或保持隔离字线处于所需电压电平的补充电压提供器。
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公开(公告)号：US09276200B2
公开(公告)日：2016-03-01
申请号：US14521213
申请日：2014-10-22
发明人： Phillip Mather , Jon Slaughter , Nicholas Rizzo
CPC分类号： H01L43/02 , G01R33/098 , H01L27/22 , H01L43/08 , H01L43/12
摘要： A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout. The X and Y pitch of the sense elements are arranged such that the line segment that stabilizes, for example, the right side of one sense element; also stabilizes the left side of the adjacent sense element.
摘要翻译： 磁传感器包括多个组，每个组包括多个磁隧道结（MTJ）装置，其具有多个导体，其被配置成并联连接一组内的MTJ装置，并且该组可串联实现材料电阻的独立优化 面积（RA），并设置总的器件电阻，使得总的桥接电阻不是很高，以至于Johnson噪声成为限制信号的关键，而不是那么低，使得CMOS元件可能会削弱读取信号。 或者，串联的至少两组中的每一个中的磁隧道结装置和并联的至少两个组，导致电连接路径的单独配置和参考层的磁参考方向，导致两者的独立优化 功能，以及更多设备设计和布局自由。 感测元件的X和Y间距被布置成使得例如稳定一个感测元件的右侧的线段; 也稳定了相邻感测元件的左侧。
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公开(公告)号：US09269891B2
公开(公告)日：2016-02-23
申请号：US13972637
申请日：2013-08-21
发明人： Renu Whig , Philip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
CPC分类号： H01L43/12 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H01L27/22 , H01L43/02 , H01L43/08
摘要： A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
摘要翻译： 半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。 该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。
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