公开(公告)号：US11830546B2

公开(公告)日：2023-11-28

申请号：US17203385

申请日：2021-03-16

Applicant: VERVAIN, LLC

Inventor： G. R. Mohan Rao

IPC: G11C11/56 ,  G06F12/02 ,  G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G11C29/00 ,  G11C16/16

CPC classification number: G11C11/5635 ,  G06F11/1068 ,  G06F11/1072 ,  G06F12/0246 ,  G11C11/5621 ,  G11C11/5678 ,  G11C16/16 ,  G11C16/3495 ,  G11C29/52 ,  G11C29/76 ,  G06F2212/7202 ,  G11C2211/5641

Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.

公开(公告)号：US20230368850A1

公开(公告)日：2023-11-16

申请号：US17741074

申请日：2022-05-10

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Bo Lei ,  Jun Wan

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3445 ,  G11C16/3495 ,  G11C16/16 ,  G11C16/26 ,  G11C16/08

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.

公开(公告)号：US11817153B2

公开(公告)日：2023-11-14

申请号：US17503197

申请日：2021-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Ilhan Park ,  Youngdeok Seo ,  Dongmin Shin

IPC: G11C16/16 ,  G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/16 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.

公开(公告)号：US11810630B2

公开(公告)日：2023-11-07

申请号：US17523523

申请日：2021-11-10

Applicant: Micron Technology, Inc.

Inventor： Amit Bhardwaj

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G06N20/00 ,  G11C29/18 ,  G11C16/26 ,  G06F18/21 ,  G06F18/243

CPC classification number: G11C16/3495 ,  G06F18/2178 ,  G06F18/24323 ,  G06N20/00 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26 ,  G11C29/18

Abstract: An on-chip copy command is detected. The on-chip copy command comprises a source address referencing a plane of a memory device, and a destination address referencing the plane. A read verify relevance is estimated by processing, by a machine learning mode, one or more parameters associated with data stored at the source address. Responsive to determining that the read verify relevance satisfies a threshold condition, the on-chip copy command is performed.

公开(公告)号：US11810621B2

公开(公告)日：2023-11-07

申请号：US17458795

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Robert W. Strong ,  William Akin ,  Jeremy Binfet

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/16 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

Abstract: A method includes receiving signaling indicative of performance of a sanitization operation to a processing device coupled to a memory device and applying a sanitization voltage to a plurality of memory blocks of the memory device. The sanitization voltage can be greater than an erase voltage of the plurality of memory blocks.

公开(公告)号：US20230335198A1

公开(公告)日：2023-10-19

申请号：US18299332

申请日：2023-04-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirofumi HEBISHIMA

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/32

CPC classification number: G11C16/16 ,  G11C16/3413 ,  G11C16/32

Abstract: A semiconductor device having an electrically writable or erasable non-volatile memory and a control circuit for executing mode control of a write operation and an erase operation of the non-volatile memory, in which the non-volatile memory has a rewrite suspension/recovery control circuit: responding to a suspension request signal from the control unit that requests a suspension of a rewrite operation; responding to an operation for suspending an application of a write voltage or an erase voltage and a recovery request signal from the control unit that requests a recovery from the suspension of the rewrite operation; controlling an operation for recovery from the suspension of the voltage application; and outputting a rewrite interruption/return control circuit that outputs to the control circuit a voltage application stop flag at a voltage application stop of the write voltage or erase voltage, and a rewrite information holding circuit that holds write position information for identifying a selection line to which a write voltage is applied at a response time of a suspension request signal.

公开(公告)号：US11791000B2

公开(公告)日：2023-10-17

申请号：US17859926

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Kishore K. Muchherla

IPC: G06F12/02 ,  G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G06F12/0246 ,  G06F12/0253 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3495 ,  G06F2212/7202

Abstract: A method includes determining a first valid translation unit count (VTC) for a first block of memory cells, determining a second VTC for a second block of memory cells when the first VTC is below a VTC threshold corresponding to performance of a memory management operation, consolidating the first VTC and the second VTC when the consolidated first VTC and the second VTC equal or exceed the VTC threshold corresponding to the performance of the memory management operation, and executing the memory management operation utilizing the consolidated first VTC and the second VTC.

公开(公告)号：US11790208B2

公开(公告)日：2023-10-17

申请号：US17238077

申请日：2021-04-22

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G06N3/04 ,  G11C11/54 ,  G06N3/063 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06N3/045 ,  G06N3/063 ,  G11C11/54 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3436 ,  G11C29/38

Abstract: A number of circuits for use in an output block coupled to a non-volatile memory array in a neural network are disclosed. The embodiments include a circuit for converting an output current from a neuron in a neural network into an output voltage, a circuit for converting a voltage received on an input node into an output current, a circuit for summing current received from a plurality of neurons in a neural network, and a circuit for summing current received from a plurality of neurons in a neural network.

公开(公告)号：US20230317183A1

公开(公告)日：2023-10-05

申请号：US17881012

申请日：2022-08-04

Applicant: SK hynix Inc.

Inventor： Byoung Sung YOU

IPC: G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  G11C7/10

CPC classification number: G11C16/3459 ,  G11C7/1039 ,  G11C16/102 ,  G11C16/16 ,  G11C16/26

Abstract: A semiconductor memory device includes a plurality of memory blocks, a peripheral circuit, control logic, and a status checker. Each of the plurality of memory blocks includes a plurality of physical pages. The peripheral circuit is configured to perform a program operation, an erase operation, or a read operation on a selected memory block among the plurality of memory blocks. The control logic controls the program operation, the erase operation, or the read operation of the peripheral circuit. The status checker checks a ratio of a programmed page among the physical pages included in the plurality of memory blocks.

公开(公告)号：US20230307073A1

公开(公告)日：2023-09-28

申请号：US17890784

申请日：2022-08-18

Applicant: SK hynix Inc.

Inventor： Gil Bok CHOI ,  Moon Sik SEO ,  Dae Hwan YUN

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/3495 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16

Abstract: A memory system and a method of operating the memory system are provided. The memory system includes a plurality of semiconductor memory devices each of which includes a plurality of memory blocks. The memory system also includes a controller configured to control the plurality of semiconductor memory devices to perform a program operation, a read operation, and an operation of removing a hole in a space region on a target memory block of the plurality of memory blocks. The controller controls the plurality of semiconductor memory devices to perform the operation of removing the hole in the space region on the target memory block when an erase count of the target memory block of the plurality of memory blocks is greater than a set value.