公开(公告)号：US20170294362A1

公开(公告)日：2017-10-12

申请号：US15630112

申请日：2017-06-22

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Yusheng LIN ,  Chee Hiong CHEW ,  Francis J. CARNEY

IPC分类号： H01L23/055 ,  H01R4/48 ,  H01L23/50 ,  H01L23/10 ,  H01L23/057

CPC分类号： H01L23/055 ,  H01L21/50 ,  H01L23/041 ,  H01L23/053 ,  H01L23/057 ,  H01L23/10 ,  H01L23/4006 ,  H01L23/492 ,  H01L23/49811 ,  H01L23/49844 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/45 ,  H01L24/48 ,  H01L24/72 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/72 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01R4/4863 ,  H01R4/489 ,  H01L2924/00012 ,  H01L2924/00014

摘要： Implementations of semiconductor packages may include: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die, wherein the pin includes a reversibly elastically deformable lower portion configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate.

公开(公告)号：US20170288564A1

公开(公告)日：2017-10-05

申请号：US15467218

申请日：2017-03-23

申请人： Keihin Corporation

发明人： Takashi Ishii ,  Shinya Saito

IPC分类号： H02M7/00 ,  H02M7/537 ,  H05K1/18 ,  H01L21/48 ,  H01L23/373 ,  H01L23/495 ,  H01L23/00 ,  H02P27/06 ,  H05K3/34

CPC分类号： H02M7/003 ,  H01L21/4825 ,  H01L21/4853 ,  H01L23/053 ,  H01L23/3735 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49811 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/40 ,  H01L2224/83815 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/1425 ,  H01L2924/19107 ,  H01L2924/37001 ,  H02M7/537 ,  H02P27/06 ,  H05K1/0306 ,  H05K1/053 ,  H05K1/181 ,  H05K3/341 ,  H05K2201/10166 ,  H05K2201/10174 ,  H05K2201/1053

摘要： A second lead frame is set onto a conductive layer and a busbar. The second lead frame has holes previously formed at opposite ends thereof, and pieces of solder material or solder pieces are inserted into the holes. Then, the solder pieces are vibrated by an ultrasonically vibrating tool, whereby the solder pieces are melted without having a high temperature. The second lead frame is thus bonded to the conductive layer and the busbar. A semiconductor element and the busbar are connected by a first lead frame and the second lead frame. The connection structure thereof is such that the second lead frame to be bonded by ultrasonic bonding or other bonding methods is not directly in contact with the semiconductor element, which eliminates the risk of damage to the semiconductor element.

公开(公告)号：US20170284951A1

公开(公告)日：2017-10-05

申请号：US15086573

申请日：2016-03-31

申请人： Infineon Technologies AG

发明人： Stephan Pindl ,  Daniel Lugauer ,  Dominic Maier ,  Alfons Dehe

IPC分类号： G01N27/02 ,  H01L21/56 ,  H01L23/538 ,  H05K1/18 ,  H01L23/31

CPC分类号： H01L23/315 ,  G01N27/028 ,  G01N27/128 ,  G01N33/0036 ,  H01L21/185 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/561 ,  H01L21/568 ,  H01L21/7624 ,  H01L23/053 ,  H01L23/057 ,  H01L23/291 ,  H01L23/295 ,  H01L23/296 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/24 ,  H01L24/96 ,  H01L33/0079 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3025 ,  H05K1/181

摘要： According to an embodiment, a sensor package includes an electrically insulating substrate including a cavity in the electrically insulating substrate, an ambient sensor, an integrated circuit die embedded in the electrically insulating substrate, and a plurality of conductive interconnect structures coupling the ambient sensor to the integrated circuit die. The ambient sensor is supported by the electrically insulating substrate and arranged adjacent the cavity.

公开(公告)号：US20170283144A1

公开(公告)日：2017-10-05

申请号：US15459420

申请日：2017-03-15

申请人： Infineon Technologies AG

发明人： Franco Mariani ,  Christoph Ahamer ,  Corneleus Esguerra Caunan

IPC分类号： B65D73/02 ,  H01L23/10 ,  H01L23/053

CPC分类号： B65D73/02 ,  H01L23/053 ,  H01L23/10 ,  H01L24/75 ,  H01L2224/75601 ,  H05K13/0084

摘要： A carrier tape comprises a flexible body portion having a top surface. The flexible body portion comprises a plurality of pockets. Each of the plurality of pockets comprises pocket side walls, a base bottom portion fully circulating a raised bottom portion of a pedestal. The pedestal is made up of the raised bottom portion and pedestal side walls. The pedestal sidewalls, the base bottom portion and a lower part of the pocket side walls constitute a trench fully circulating the pedestal.

公开(公告)号：US20170271306A1

公开(公告)日：2017-09-21

申请号：US15614056

申请日：2017-06-05

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Chong WANG ,  Hai Fang ZHANG ,  Xuan Jie LIU

IPC分类号： H01L25/04 ,  H01L23/053 ,  H01L23/64 ,  H01L23/12 ,  H01L51/00 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L25/043 ,  H01L21/76898 ,  H01L23/053 ,  H01L23/12 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/64 ,  H01L24/743 ,  H01L51/0017

摘要： A packaging structure and a packaging method are provided. The packaging structure includes a carrier semiconductor structure including a carrier substrate, a carrier dielectric layer, and a carrier top conductive layer inside the carrier dielectric layer and having a top exposed by the carrier dielectric layer. The packaging structure also includes a top semiconductor structure including a top substrate, a first dielectric layer, a zeroth conductive layer, and a second dielectric layer, wherein a position of the zeroth conductive layer corresponds to a position of the carrier top conductive layer. Further, the packaging structure includes a conductive plug formed on one side of the zeroth conductive layer, and penetrating through the top substrate, the first dielectric layer, and the second dielectric layer, wherein the conductive plug is electrically connected to each of the zeroth conductive layer and the carrier top conductive layer.

公开(公告)号：US20170271224A1

公开(公告)日：2017-09-21

申请号：US15452118

申请日：2017-03-07

申请人： FUJI ELECTRIC CO., LTD.

发明人： Yuichiro HINATA

IPC分类号： H01L23/16 ,  H01L23/053 ,  H01L25/11

CPC分类号： H01L23/16 ,  H01L21/566 ,  H01L23/053 ,  H01L23/3121 ,  H01L23/49833 ,  H01L24/29 ,  H01L24/32 ,  H01L25/072 ,  H01L25/115 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/014 ,  H01L2924/00014

摘要： A semiconductor device, including a plurality of semiconductor units disposed in a matrix, and a capsule encapsulating the plurality of semiconductor units. Each semiconductor unit includes a semiconductor element and another capsule encapsulating the semiconductor element. Each semiconductor unit further has a plurality of convex portions formed on a front surface thereof, and an engagement portion through which the semiconductor unit engages with at least one of the other semiconductor units.

公开(公告)号：US20170263571A1

公开(公告)日：2017-09-14

申请号：US15453964

申请日：2017-03-09

申请人： IBIDEN CO., LTD.

发明人： Teruyuki ISHIHARA ,  Hiroyuki BAN ,  Kosuke IKEDA ,  Haiying MEI

IPC分类号： H01L23/552 ,  H01L21/768 ,  H01L23/053 ,  H01L23/48

CPC分类号： H01L23/552 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/053 ,  H01L23/295 ,  H01L23/481 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16237 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

摘要： An electronic component built-in substrate includes an insulating substrate having a through hole and an inner wall surrounding the through hole, an electronic component accommodated in the through hole of the substrate, a sealing member filling the through hole such that the sealing member is covering the electronic component in the through hole of the substrate and exposing a terminal of the electronic component on a first side of the substrate, and a shield layer structure including a first metal film and a second metal film formed such that the first metal film is formed on the inner wall of the substrate and surrounding the through hole of the substrate and that the second metal film is formed on a second side of the substrate on the opposite side with respect to the first side and covering an opening of the through hole on the second side of the substrate.

公开(公告)号：US20170263515A1

公开(公告)日：2017-09-14

申请号：US15066397

申请日：2016-03-10

申请人： ANALOG DEVICES, INC.

发明人： David Bolognia ,  Jingwen Zhu

IPC分类号： H01L23/053 ,  H01L23/16

CPC分类号： H01L23/053 ,  H01L23/10 ,  H01L24/06 ,  H01L2924/16195

摘要： Semiconductor packages and methods of manufacturing semiconductor packages are described herein. In certain embodiments, the semiconductor package includes a substrate, a wall attached to the substrate, a first adhesive layer disposed between a bottom surface of the wall and a top surface of the substrate, and a second adhesive layer disposed around an outer perimeter of the first adhesive layer, the second adhesive layer disposed adjacent and contacting the wall, the second adhesive layer different from the first adhesive layer, wherein at least one of the first adhesive layer and the second adhesive layer connects the wall to electrical ground.

公开(公告)号：US09741666B1

公开(公告)日：2017-08-22

申请号：US15333433

申请日：2016-10-25

申请人： MACOM Technology Solutions Holdings, Inc.

发明人： Emmanuelle R. O. Convert ,  Ryan M. Clement ,  Simon J. Mahon

IPC分类号： H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66

CPC分类号： H01L23/552 ,  H01L21/4817 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/56 ,  H01L22/14 ,  H01L23/04 ,  H01L23/053 ,  H01L23/315 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6683 ,  H01L2224/04042 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/50 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10271 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/10336 ,  H01L2924/1423 ,  H01L2924/16152 ,  H01L2924/1617 ,  H01L2924/16251 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2224/05599 ,  H01L2224/85399

摘要： An apparatus includes a package, a wall and a lid. The package may be configured to mount two chips configured to generate one or more signals in a millimeter-wave frequency range. The wall may be formed between the two chips. The wall generally has a plurality of conductive arches that attenuate an electromagnetic coupling between the two chips in the millimeter-wave frequency range. The lid may be configured to enclose the chips to form a cavity.

公开(公告)号：US20170194296A1

公开(公告)日：2017-07-06

申请号：US15231444

申请日：2016-08-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Katsuhiro YASUI

IPC分类号： H01L25/07 ,  H01L23/04 ,  H01L23/00 ,  H01L23/29 ,  H01L25/00

CPC分类号： H01L25/072 ,  H01L23/041 ,  H01L23/053 ,  H01L23/24 ,  H01L23/28 ,  H01L23/29 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48227 ,  H01L2224/49052 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85399

摘要： A semiconductor module includes an insulating substrate. A first and a second metal member are joined respectively to a side surface of the substrate. Each metal member has an opening formed therein. A first and a second conductive layer are on the upper surface of the substrate and spaced apart from each other. A first semiconductor chip is mounted on the first conductive layer. A first electrode of the first semiconductor chip is electrically connected to the first conductive layer, and a second electrode is electrically connected to the second conductive layer. A first terminal is electrically connected to the first conductive layer, and a second terminal is electrically connected to the second conductive layer. A sealing resin is disposed on the upper surface of the substrate to cover the first conductive layer, the second conductive layer, the first semiconductor chip, and portions of the first and second terminals.