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公开(公告)号：US20240355388A1
公开(公告)日：2024-10-24
申请号：US18758901
申请日：2024-06-28
Inventor： Yu-Der Chih , Jonathan Tsung-Yung Chang , Yun-Sheng Chen , Maybe Chen , Ya-Chin King , Wen Zhang Lin , Chrong Jung Lin , Hsin-Yuan Yu
CPC classification number: G11C13/004 , G11C13/0069 , H10B63/30 , H10N70/253 , G11C2013/0045 , G11C2013/0078
Abstract: Disclosed herein are related to a memory cell including one or more programmable resistors and a control transistor. In one aspect, a programmable resistor includes a gate structure and one or more source/drain structures for forming a transistor. A resistance of the programmable resistor may be set by applying a voltage to the gate structure, while the control transistor is enabled. Data stored by the programmable resistor can be read by sensing current through the programmable resistor, while the control transistor is disabled. In one aspect, the one or more programmable resistors and the control transistor are implemented by same type of components, allowing the memory cell to be formed in a compact manner through a simplified the fabrication process.
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公开(公告)号：US20240354548A1
公开(公告)日：2024-10-24
申请号：US18302154
申请日：2023-04-18
Inventor： Kerem Akarvardar , Yu-Der Chih , Xiaoyu Sun
IPC: G06N3/0442 , G06N3/048
CPC classification number: G06N3/0442 , G06N3/048
Abstract: Systems and methods are provided for a neural network that includes a multiply accumulate (MAC) unit that is configured to receive an input vector weight matrix; multiply the input matrix by the input vector weight matrix, generating input vector partial sums; receive time-delayed hidden vectors and a hidden vector weight matrix; and multiply the time-delayed hidden vectors and the hidden vector weight matrix, which generates hidden vector partial sums. An accumulator may be coupled to the MAC unit and configured to accumulate and add the input vector partial sums and the hidden vector partial sums, generating full sum vectors. The neural network may generate the time-delayed hidden vectors based on the full sum vectors. The neural network may further include a first selection device coupled to the MAC unit that is configured to select between the input matrix and the time-delayed hidden vectors for reception at the MAC unit.
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公开(公告)号：US20240257870A1
公开(公告)日：2024-08-01
申请号：US18630241
申请日：2024-04-09
Inventor： Zheng-Jun Lin , Chung-Cheng Chou , Yu-Der Chih , Pei-Ling Tseng
IPC: G11C13/00
CPC classification number: G11C13/0064 , G11C13/003 , G11C13/004
Abstract: The disclosed invention presents a self-tracking reference circuit that compensates for IR drops and achieves the target resistance state at different temperatures after write operations. The disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track PVT variations to provide a PVT tracking level for RRAM verify operation.
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公开(公告)号：US20240249780A1
公开(公告)日：2024-07-25
申请号：US18628483
申请日：2024-04-05
Inventor： Chung-Chieh Chen , Cheng-Hsiung Kuo , Yu-Der Chih
Abstract: A sense amplifier control system includes a precharge control switch configured to receive a precharge signal. A reference cell is configured to receive a reference word line signal. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.
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65.发明授权公开(公告)号：US12026404B2
公开(公告)日：2024-07-02
申请号：US18313374
申请日：2023-05-08
Inventor： Hiroki Noguchi , Shih-Lien Linus Lu , Yu-Der Chih , Yih Wang
CPC classification number: G06F3/0659 , G06F1/28 , G06F3/0604 , G06F3/0673 , G06F9/4893
Abstract: A memory device including a memory array with a plurality of memory macros, a power supplying circuit, and a controller is provided. The power supplying circuit is coupled to the memory array. The controller is coupled to the memory array. The power supplying circuit is configured to provide power to perform write operations to a number of the memory macros at the same time. The number of the memory macros for the write operations performed at the same time is not higher than a maximum number of the memory macros. The controller obtains the maximum number of the memory macros for the write operations performed at the same time by the power supplying circuit. The controller re-arranges a schedule for a sequence of the write operations of the memory macros to generate a re-arranged schedule. The maximum number is taken as a threshold value. In the re-arranged schedule, a number of part of the memory macros for the write operations performed at the same time is equal to or less then the threshold value.
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Patent Agency Ranking
公开(公告)号：US20240046968A1
公开(公告)日：2024-02-08
申请号：US18447872
申请日：2023-08-10
Inventor： Chia-Fu Lee , Hon-Jarn Lin , Yu-Der Chih
IPC: G11C7/06
CPC classification number: G11C7/062 , G11C2207/063
Abstract: A sense amplifier is provided. A first terminal of a first invertor is connected to a power node and a second terminal of the first invertor is connected to a cell current source. A first terminal of a second invertor is connected to the power node and a second terminal of the second invertor is connected to a reference current source. The first invertor is cross coupled with the second invertor at a first node and a second node. A pre-charge circuit is connected to the first node and the second node. A first pull up transistor and a second pull up transistor are connected between a supply voltage node and the power node. A signal level detector circuit is connected to the second pull up transistor. The signal level detector circuit switches on the second pull up transistor when a remaining voltage on one of the first node and the second node is below a reference voltage.
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公开(公告)号：US20230352071A1
公开(公告)日：2023-11-02
申请号：US18169560
申请日：2023-02-15
Inventor： Po-Hao Lee , Yi-Chun Shih , Chia-Fu Lee , Yu-Der Chih
IPC: G11C11/16
CPC classification number: G11C11/1673 , G11C11/1659
Abstract: A semiconductor device and a method of operating the semiconductor device are disclosed. In one aspect, the semiconductor device includes a plurality of memory cells, a first reference cell connected to a first subset of the plurality of memory cells via a first common source line, and a second reference cell connected to a second subset of the plurality of memory storage cells via a second common source line. The semiconductor device also includes a sense amplifier configured to, when reading from a first memory cell of the first subset, receive an output from the second reference cell and an output from the first memory cell.
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公开(公告)号：US11735238B2
公开(公告)日：2023-08-22
申请号：US17855107
申请日：2022-06-30
Inventor： Chien-An Lai , Chung-Cheng Chou , Yu-Der Chih
CPC classification number: G11C7/222 , G11C7/106 , G11C7/1087 , G11C7/14 , G11C13/004 , G11C13/0026 , G11C13/0038 , G11C13/0069
Abstract: A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.
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公开(公告)号：US20230260559A1
公开(公告)日：2023-08-17
申请号：US18138305
申请日：2023-04-24
Inventor： Yu-Der Chih
CPC classification number: G11C7/20 , G06F11/1469 , G11C11/4072 , G06F11/3058 , G06F1/30 , G06F11/3037 , G11C5/148
Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.
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公开(公告)号：US11720130B2
公开(公告)日：2023-08-08
申请号：US17397542
申请日：2021-08-09
Inventor： Yen-An Chang , Chieh-Pu Lo , Yi-Chun Shih , Chia-Fu Lee , Yu-Der Chih
CPC classification number: G05F1/575 , G11C11/1697
Abstract: A power regulation system including a reference generator, a temperature compensation circuit coupled to the reference generator, and a low-dropout (LDO) regulator circuit coupled to the temperature compensation circuit, wherein the temperature compensation circuit provides a reference voltage to the LDO regulator circuit at least based on a ratio of a first current and a second current.
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