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公开(公告)号：US20240354548A1
公开(公告)日：2024-10-24
申请号：US18302154
申请日：2023-04-18
Inventor： Kerem Akarvardar , Yu-Der Chih , Xiaoyu Sun
IPC: G06N3/0442 , G06N3/048
CPC classification number: G06N3/0442 , G06N3/048
Abstract: Systems and methods are provided for a neural network that includes a multiply accumulate (MAC) unit that is configured to receive an input vector weight matrix; multiply the input matrix by the input vector weight matrix, generating input vector partial sums; receive time-delayed hidden vectors and a hidden vector weight matrix; and multiply the time-delayed hidden vectors and the hidden vector weight matrix, which generates hidden vector partial sums. An accumulator may be coupled to the MAC unit and configured to accumulate and add the input vector partial sums and the hidden vector partial sums, generating full sum vectors. The neural network may generate the time-delayed hidden vectors based on the full sum vectors. The neural network may further include a first selection device coupled to the MAC unit that is configured to select between the input matrix and the time-delayed hidden vectors for reception at the MAC unit.
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2.发明公开公开(公告)号：US20240013042A1
公开(公告)日：2024-01-11
申请号：US17859721
申请日：2022-07-07
Inventor： Xiaoyu Sun , Kerem Akarvardar
CPC classification number: G06N3/08 , G06F7/5443
Abstract: Systems and methods for a pipelined heterogeneous dataflow for an artificial intelligence accelerator are disclosed. A pipelined processing core includes a first processing core configured to have a first type of dataflow and a second processing core configured to have a second type of dataflow. The first processing core includes a matrix array of PEs arranged in columns and rows, each of the PEs configured to perform a MAC operation based on an input and a weight. The second processing core is configured to receive an output from the first processing core. The second processing core includes a column of PEs configured to perform MAC operations.
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公开(公告)号：US12210756B2
公开(公告)日：2025-01-28
申请号：US17740378
申请日：2022-05-10
Inventor： Xiaoyu Sun , Kerem Akarvardar , Rawan Naous
IPC: G06F3/06
Abstract: A memory system, an operating method and a controller are provided. The memory system comprises a memory array and a controller. The memory array comprises a probing memory block and a plurality of memory blocks. The controller is configured to perform; write a probing data to the probing memory block; detect a strength of the probing data from the probing memory block to obtain an aging condition of the memory array; and control each memory block to be enabled or disabled according to the aging condition.
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公开(公告)号：US20230368014A1
公开(公告)日：2023-11-16
申请号：US17740367
申请日：2022-05-10
Inventor： Kerem Akarvardar , Rawan Naous , Xiaoyu Sun
CPC classification number: G06N3/08 , G06K9/6262 , G06K9/6277 , G06K9/628
Abstract: A design method, an operating method and an electronic system are provided. The method comprises receiving a training dataset having a plurality of training data, wherein each training data is labeled to one of a plurality of classes; selecting at least one first class from the plurality of classes and establishing a first category having the at least one selected first class; training a first model with the training dataset, and using the at least one first class within the first category for verification; and implementing the first model on the accelerator.
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公开(公告)号：US11901004B2
公开(公告)日：2024-02-13
申请号：US17715964
申请日：2022-04-08
Inventor： Kerem Akarvardar , Win-San Khwa , Rawan Naous , Jin Cai , Meng-Fan Chang , Hon-Sum Philip Wong
CPC classification number: G11C13/0069 , G06F17/16 , G11C13/0004 , G11C2213/15
Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.
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Patent Agency Ranking
公开(公告)号：US20230229922A1
公开(公告)日：2023-07-20
申请号：US17577014
申请日：2022-01-17
Inventor： Xiaoyu Sun , Kerem Akarvardar , Rawan Naous
CPC classification number: G06N3/082 , G06N3/04 , G06F11/073
Abstract: A training method, an operating method and a memory system are provided. The operating method comprises using a first memory block of the memory system for computation; obtaining an aging condition of the memory system; determining whether the aging condition meets a predetermined aging condition; and when it is determined that the aging condition meets the predetermined aging condition, enabling the second memory block and using the first memory block and the second memory block for computation.
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公开(公告)号：US20230367497A1
公开(公告)日：2023-11-16
申请号：US17740378
申请日：2022-05-10
Inventor： Xiaoyu Sun , Kerem Akarvardar , Rawan Naous
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0659 , G06F3/0619 , G06F3/0679
Abstract: A memory system, an operating method and a controller are provided. The memory system comprises a memory array and a controller. The memory array comprises a probing memory block and a plurality of memory blocks. The controller is configured to perform; write a probing data to the probing memory block; detect a strength of the probing data from the probing memory block to obtain an aging condition of the memory array; and control each memory block to be enabled or disabled according to the aging condition.
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公开(公告)号：US20230133360A1
公开(公告)日：2023-05-04
申请号：US17825036
申请日：2022-05-26
Inventor： Rawan Naous , Kerem Akarvardar , Mahmut Sinangil , Yu-Der Chih , Saman Adham , Nail Etkin Can Akkaya , Hidehiro Fujiwara , Yih Wang , Jonathan Tsung-Yung Chang
Abstract: Systems and methods for floating-point processors and methods for operating floating-point processors are provided. A floating-point processor includes a quantizer, a compute-in-memory device, and a decoder. The floating-processor is configured to receive an input array in which the values of the input array are represented in floating-point format. The floating-point processor may be configured to convert the floating-point numbers into integer format so that multiply-accumulate operations can be performed on the numbers. The multiply-accumulate operations generate partial sums, which are in integer format. The partial sums can be accumulated until a full sum is achieved, wherein the full sum can then be converted to floating-point format.
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公开(公告)号：US20230377614A1
公开(公告)日：2023-11-23
申请号：US18357769
申请日：2023-07-24
Inventor： Qing Dong , Mahmut Sinangil , Yen-Ting Lin , Kerem Akarvardar , Carlos H. Diaz , Yih Wang
CPC classification number: G11C7/08 , G11C7/1012 , G11C16/26 , G11C5/06 , G11C13/004
Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
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公开(公告)号：US20230326525A1
公开(公告)日：2023-10-12
申请号：US17715964
申请日：2022-04-08
Inventor： Kerem Akarvardar , Win-San Khwa , Rawan Naous , Jin Cai , Meng-Fan Chang , Hon-Sum Philip Wong
CPC classification number: G11C13/0069 , G06F17/16 , G11C13/0004 , G11C2213/15
Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.
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