公开(公告)号：US20230326525A1

公开(公告)日：2023-10-12

申请号：US17715964

申请日：2022-04-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kerem Akarvardar ,  Win-San Khwa ,  Rawan Naous ,  Jin Cai ,  Meng-Fan Chang ,  Hon-Sum Philip Wong

IPC: G11C13/00 ,  G06F17/16

CPC classification number: G11C13/0069 ,  G06F17/16 ,  G11C13/0004 ,  G11C2213/15

Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.

公开(公告)号：US20230367497A1

公开(公告)日：2023-11-16

申请号：US17740378

申请日：2022-05-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xiaoyu Sun ,  Kerem Akarvardar ,  Rawan Naous

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0659 ,  G06F3/0619 ,  G06F3/0679

Abstract: A memory system, an operating method and a controller are provided. The memory system comprises a memory array and a controller. The memory array comprises a probing memory block and a plurality of memory blocks. The controller is configured to perform; write a probing data to the probing memory block; detect a strength of the probing data from the probing memory block to obtain an aging condition of the memory array; and control each memory block to be enabled or disabled according to the aging condition.

公开(公告)号：US20230133360A1

公开(公告)日：2023-05-04

申请号：US17825036

申请日：2022-05-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rawan Naous ,  Kerem Akarvardar ,  Mahmut Sinangil ,  Yu-Der Chih ,  Saman Adham ,  Nail Etkin Can Akkaya ,  Hidehiro Fujiwara ,  Yih Wang ,  Jonathan Tsung-Yung Chang

IPC: G06F9/30 ,  G06F9/355

Abstract: Systems and methods for floating-point processors and methods for operating floating-point processors are provided. A floating-point processor includes a quantizer, a compute-in-memory device, and a decoder. The floating-processor is configured to receive an input array in which the values of the input array are represented in floating-point format. The floating-point processor may be configured to convert the floating-point numbers into integer format so that multiply-accumulate operations can be performed on the numbers. The multiply-accumulate operations generate partial sums, which are in integer format. The partial sums can be accumulated until a full sum is achieved, wherein the full sum can then be converted to floating-point format.

公开(公告)号：US11901004B2

公开(公告)日：2024-02-13

申请号：US17715964

申请日：2022-04-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kerem Akarvardar ,  Win-San Khwa ,  Rawan Naous ,  Jin Cai ,  Meng-Fan Chang ,  Hon-Sum Philip Wong

IPC: G11C13/00 ,  G06F17/16

CPC classification number: G11C13/0069 ,  G06F17/16 ,  G11C13/0004 ,  G11C2213/15

Abstract: A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.

公开(公告)号：US20240028869A1

公开(公告)日：2024-01-25

申请号：US17870053

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xiaoyu Sun ,  Rawan Naous ,  Murat Kerem Akarvardar

IPC: G06N3/04

CPC classification number: G06N3/0445

Abstract: A reconfigurable processing circuit of an AI accelerator and a method of operating the same are disclosed. In one aspect, the reconfigurable processing circuit includes a first memory configured to store an input activation state, a second memory configured to store a weight, a multiplier configured to multiply the weight and the input activation state and output a product, a first multiplexer (mux) configured to, based on a first selector, output a previous sum from a previous reconfigurable processing element, a third memory configured to store a first sum, a second mux configured to, based on a second selector, output the previous sum or the first sum, an adder configured to add the product and the previous sum or the first sum to output a second sum, and a third mux configured to, based on a third selector, output the second sum or the previous sum.

公开(公告)号：US20230229922A1

公开(公告)日：2023-07-20

申请号：US17577014

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xiaoyu Sun ,  Kerem Akarvardar ,  Rawan Naous

IPC: G06N3/08 ,  G06N3/04 ,  G06F11/07

CPC classification number: G06N3/082 ,  G06N3/04 ,  G06F11/073

Abstract: A training method, an operating method and a memory system are provided. The operating method comprises using a first memory block of the memory system for computation; obtaining an aging condition of the memory system; determining whether the aging condition meets a predetermined aging condition; and when it is determined that the aging condition meets the predetermined aging condition, enabling the second memory block and using the first memory block and the second memory block for computation.

公开(公告)号：US12210756B2

公开(公告)日：2025-01-28

申请号：US17740378

申请日：2022-05-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Xiaoyu Sun ,  Kerem Akarvardar ,  Rawan Naous

IPC: G06F3/06

Abstract: A memory system, an operating method and a controller are provided. The memory system comprises a memory array and a controller. The memory array comprises a probing memory block and a plurality of memory blocks. The controller is configured to perform; write a probing data to the probing memory block; detect a strength of the probing data from the probing memory block to obtain an aging condition of the memory array; and control each memory block to be enabled or disabled according to the aging condition.

公开(公告)号：US20230368014A1

公开(公告)日：2023-11-16

申请号：US17740367

申请日：2022-05-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kerem Akarvardar ,  Rawan Naous ,  Xiaoyu Sun

IPC: G06N3/08 ,  G06K9/62

CPC classification number: G06N3/08 ,  G06K9/6262 ,  G06K9/6277 ,  G06K9/628

Abstract: A design method, an operating method and an electronic system are provided. The method comprises receiving a training dataset having a plurality of training data, wherein each training data is labeled to one of a plurality of classes; selecting at least one first class from the plurality of classes and establishing a first category having the at least one selected first class; training a first model with the training dataset, and using the at least one first class within the first category for verification; and implementing the first model on the accelerator.