公开(公告)号：US12040285B2

公开(公告)日：2024-07-16

申请号：US17461391

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chen Lai ,  Ming-Chih Yew ,  Po-Yao Lin ,  Yu-Sheng Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/3185 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/73204

Abstract: A package structure and a formation method of a package structure are provided. The package structure includes a circuit substrate and a die package bonded to the circuit substrate through bonding structures. The package structure also includes a reinforcing structure over the circuit substrate. The reinforcing structure partially surrounds a corner of the die package. The package structure further includes an underfill structure surrounding the bonding structure. The underfill structure is in direct contact with the reinforcing structure.

公开(公告)号：US12014969B2

公开(公告)日：2024-06-18

申请号：US17460836

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Chen Lai ,  Ming-Chih Yew ,  Li-Ling Liao ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/3178 ,  H01L21/56 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/73204 ,  H01L2924/1434 ,  H01L2924/1811 ,  H01L2924/1815 ,  H01L2924/182

Abstract: A package structure is provided. The package structure includes a redistribution structure over a substrate, a semiconductor die over the redistribution structure and electrically coupled to the substrate, and an underfill material over the substrate and encapsulating the redistribution structure and the semiconductor die. The underfill material includes an extension portion overlapping a corner of the semiconductor die and extending into the substrate.

公开(公告)号：US11830800B2

公开(公告)日：2023-11-28

申请号：US17344982

申请日：2021-06-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L21/561 ,  H01L21/568 ,  H01L2224/16225

Abstract: A metallization structure electrically connected to a conductive bump is provided. The metallization structure includes an oblong-shaped or elliptical-shaped redistribution pad, a conductive via disposed on the oblong-shaped or elliptical-shaped redistribution pad, and an under bump metallurgy covering the conductive via, wherein the conductive bump is disposed on the UBM. Furthermore, a package structure including the above-mentioned metallization structures is provided.

公开(公告)号：US20230378046A1

公开(公告)日：2023-11-23

申请号：US18361933

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L21/561

Abstract: A metallization structure electrically connected to a conductive bump is provided. The metallization structure includes an oblong-shaped or elliptical-shaped redistribution pad, a conductive via disposed on the oblong-shaped or elliptical-shaped redistribution pad, and an under bump metallurgy covering the conductive via, wherein the conductive bump is disposed on the UBM. Furthermore, a package structure including the above-mentioned metallization structures is provided.

公开(公告)号：US20230369194A1

公开(公告)日：2023-11-16

申请号：US18359898

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Chen Lai ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49816 ,  H01L24/32 ,  H01L25/18 ,  H01L2224/32225

Abstract: A semiconductor package includes a die, a first conductive pattern, a second conductive pattern and first and second under-ball metallurgy (UBM) patterns. The first conductive pattern and the second conductive pattern are disposed below and electrically connected to the die, wherein the first conductive pattern has an ellipse-like shape, and the second conductive pattern has a circular shape. The first and second under-ball metallurgy (UBM) patterns correspond to the first and second conductive patterns, the first conductive pattern has a first length, the second conductive pattern has a second length, the first and second UBM patterns have a third length, wherein the first length is larger than the third length and the second length is smaller than the third length.

公开(公告)号：US20230066370A1

公开(公告)日：2023-03-02

申请号：US17458560

申请日：2021-08-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Po-Chen Lai ,  Chin-Hua Wang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a die, a redistribution structure and a plurality of conductive terminals. The redistribution structure is disposed below and electrically connected to the die. The redistribution structure includes a plurality of conductive patterns, and at least one of the plurality of conductive patterns has a cross-section substantially parallel to the surface of the die. The cross-section has a long-axis and a short-axis, and the long-axis intersects with a center axis of the die. The conductive terminals are disposed below and electrically connected to the redistribution structure.

公开(公告)号：US11557559B2

公开(公告)日：2023-01-17

申请号：US17185992

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tsung-Yen Lee ,  Chin-Hua Wang ,  Ming-Chih Yew ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC: H01L23/00 ,  H01L23/40 ,  H01L23/16 ,  H01L23/31

Abstract: A package structure including an organic interposer substrate, a semiconductor die, conductive bumps, an underfill, and an insulating encapsulation is provided. The organic interposer substrate includes stacked organic dielectric layers and conductive wirings embedded in the stacked organic dielectric layers. The semiconductor die is disposed over and electrically connected to the conductive wirings of the organic interposer substrate, and the semiconductor die includes chamfered edges. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate through the conductive bumps. The underfill is disposed between the semiconductor die and the organic interposer substrate, wherein the underfill encapsulates the conductive bumps and is in contact with the chamfered edges of the at least one semiconductor die. The insulating encapsulation covers the organic interposer substrate and laterally encapsulates the least one semiconductor die and the underfill.

公开(公告)号：US10971461B2

公开(公告)日：2021-04-06

申请号：US16530276

申请日：2019-08-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Po-Hao Tsai ,  Po-Yao Chuang ,  Ming-Chih Yew ,  Shin-Puu Jeng

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q9/28 ,  H01Q9/04 ,  H01L21/56 ,  H01L23/00 ,  H01L23/48 ,  H01L23/31

Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

公开(公告)号：US10276548B2

公开(公告)日：2019-04-30

申请号：US15669563

申请日：2017-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Shien Chen ,  Hsiu-Jen Lin ,  Ming-Chih Yew ,  Ming-Da Cheng ,  Yi-Jen Lai ,  Yu-Tse Su ,  Sey-Ping Sun ,  Yang-Che Chen

IPC: H01L23/02 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.

公开(公告)号：US09653391B1

公开(公告)日：2017-05-16

申请号：US15198286

申请日：2016-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Ming-Chih Yew ,  Kuang-Chun Lee ,  Po-Yao Lin ,  Shyue-Ter Leu ,  Shin-Puu Jeng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3171 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05684 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor structure includes a die, a molding interfacing with the die along a first direction, wherein a coefficient of thermal expansion (CTE) mismatch is between the molding and the die, a via extending within and through the molding, an elongated member extending within the molding and at least partially along the first direction, a conductive trace over the elongated member and the die, and a dielectric between the elongated member and the conductive trace, wherein the elongated member is proximal to the die than the via.