公开(公告)号：US09812188B2

公开(公告)日：2017-11-07

申请号：US14631603

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Zhongze Wang ,  Xiaonan Chen ,  Stanley Seungchul Song ,  Choh Fei Yeap

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/20 ,  G11C11/417 ,  G11C29/02 ,  G11C29/24 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C11/419 ,  G11C7/20 ,  G11C11/417 ,  G11C29/021 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/0407 ,  G11C2029/0409 ,  G11C2029/5002

Abstract: An apparatus includes a static random-access memory and circuitry configured to initiate a corrective action associated with the static random-access memory. The corrective action may be initiated based on a number of static random-access memory cells that have a particular state responsive to a power-up of the static random-access memory.

公开(公告)号：US09806083B2

公开(公告)日：2017-10-31

申请号：US14559205

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  H01L23/528 ,  G11C5/06 ,  G11C8/14 ,  G11C11/412 ,  H01L21/768 ,  G11C8/16 ,  G11C11/418 ,  H01L27/02

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.

公开(公告)号：US09461055B2

公开(公告)日：2016-10-04

申请号：US14280213

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Zhongze Wang ,  Daniel Wayne Perry

IPC: H01L27/112 ,  G11C11/40 ,  G11C7/00 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/112 ,  G11C7/00 ,  G11C11/40 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.

Abstract translation: 提供先进的金属氮化物 - 氧化物 - 硅（MNOS）多时间可编程（MTP）存储器。 在一个示例中，装置包括两个场效应晶体管（2T场FET）金属氮化物 - 氧化物 - 硅（MNOS）MTP存储器。 2T场FET MNOS MTP存储器可以包括形成在阱上的层间电介质（ILD）氧化物区域，并将第一和第二晶体管的相应栅极与阱分离。 控制栅极位于第一和第二晶体管的各个栅极之间，并且氮化硅 - 氧化物（SiN）区域位于控制栅极的金属部分和ILD氧化物区域的一部分之间。

公开(公告)号：US09460777B2

公开(公告)日：2016-10-04

申请号：US13957485

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC: G11C11/419 ,  G11C8/16 ,  G06F17/50 ,  G11C11/412

CPC classification number: G11C11/419 ,  G06F17/5072 ,  G11C8/16 ,  G11C11/412

Abstract: A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter.

Abstract translation: 一种器件包括静态随机存取存储器（SRAM）单元和耦合到SRAM单元的输出的读缓冲器。 读缓冲器包括一个反相器和一个开关。 反相器的输入响应于SRAM单元的输出。 开关的控制端子响应于逆变器的输出。

公开(公告)号：US09449709B1

公开(公告)日：2016-09-20

申请号：US14863417

申请日：2015-09-23

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaonan Chen ,  Niladri Narayan Mojumder ,  Zhongze Wang ,  Weidan Li

IPC: G11C11/00 ,  G11C17/18 ,  G11C11/419 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/02 ,  G11C11/4125 ,  G11C11/419 ,  G11C17/146

Abstract: A volatile and one-time program (OTP) compatible asymmetric memory cell may include a first pull-up transistor having a first threshold voltage. The asymmetric memory cell may also include a second pull-up transistor having a second threshold voltage that differs from the first threshold voltage. The asymmetric memory cell may further include a switch coupled to a well of the first pull-up transistor and the second pull-up transistor to alternate between a program voltage (Vpg) and a power supply voltage. The asymmetric memory cell may also include a peripheral switching circuit to control programming of the asymmetric memory cell.

Abstract translation: 易失性和一次性程序（OTP）兼容非对称存储单元可以包括具有第一阈值电压的第一上拉晶体管。 非对称存储单元还可以包括具有不同于第一阈值电压的第二阈值电压的第二上拉晶体管。 非对称存储单元还可以包括耦合到第一上拉晶体管和第二上拉晶体管的阱的开关，以在编程电压（Vpg）和电源电压之间交替。 非对称存储单元还可以包括用于控制非对称存储单元的编程的外围开关电路。

公开(公告)号：US09396931B2

公开(公告)日：2016-07-19

申请号：US13956398

申请日：2013-08-01

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L27/1207 ,  H01L21/02365 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

Abstract: A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

Abstract translation: 形成不同材料的散热片的方法包括：提供具有顶表面的第一材料层的衬底，掩蔽衬底的第一部分，留下衬底的第二部分，蚀刻第二部分的第一开口，形成 在所述开口中的第二材料的主体到所述第一材料的所述层的顶表面的高度，去除所述掩模，以及在所述第一部分处形成所述第一材料的翅片，并在所述第二部分处形成所述第二材料的翅片 。 还公开了具有由至少两种不同材料形成的翅片的finFET器件。

公开(公告)号：US20160163713A1

公开(公告)日：2016-06-09

申请号：US14559205

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is disclosed employing a write wordline in a second metal layer, a first read wordline in a third metal layer, and a second read wordline in a fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have increased widths, which decrease wordline resistance, decrease access time, and increase performance of the SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in a first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks disposed in the first metal layer. Landing pads corresponding to the write wordline are placed on corresponding tracks disposed in the first metal layer.

Abstract translation: 公开了在单独的金属层上具有字线的静态随机存取存储器（SRAM）位单元，以提高性能。 在一个方面，公开了采用第二金属层中的写入字线，第三金属层中的第一读取字线和第四金属层中的第二读取字线的SRAM位单元。 在单独的金属层中使用字线允许字线增加宽度，这降低了字线电阻，减少了访问时间，并提高了SRAM位单元的性能。 为了在单独的金属层中采用字线，采用第一金属层中的多个轨迹。 为了将读取的字线耦合到轨道以与SRAM位单元晶体管通信，着陆焊盘设置在设置在第一金属层中的相应的轨道上。 对应于写入字线的着陆垫被放置在设置在第一金属层中的对应的轨道上。

公开(公告)号：US20160141021A1

公开(公告)日：2016-05-19

申请号：US14546980

申请日：2014-11-18

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Ping Liu ,  Kern Rim ,  Choh Fei Yeap

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C8/14 ,  G11C8/16 ,  H01L27/0688 ,  H01L27/1104

Abstract: An apparatus includes an array of bit cells that include a first row of bit cells and a second row of bit cells. The apparatus also includes a first global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus further includes a second global read word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The apparatus also includes a global write word line configured to be selectively coupled to the first row of bit cells and to the second row of bit cells. The first global read word line, the second global read word line, and the global write word line are located in a common metal layer.

Abstract translation: 一种装置包括包括第一行位单元和第二行位单元的位单元阵列。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第一全局读取字线。 该装置还包括被配置为选择性地耦合到第一行位单元和第二行位单元的第二全局读取字线。 该装置还包括全局写入字线，其被配置为选择性地耦合到第一行位单元和第二行位单元。 第一个全局读取字线，第二个全局读取字线和全局写入字线位于公共金属层中。

公开(公告)号：US20160064067A1

公开(公告)日：2016-03-03

申请号：US14468976

申请日：2014-08-26

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

IPC: G11C11/419 ,  H01L27/11 ,  H01L21/768 ,  H01L21/3213

CPC classification number: G11C11/419 ,  G11C7/18 ,  G11C8/16 ,  G11C11/40 ,  G11C11/412 ,  G11C29/816 ,  H01L21/32133 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/1104

Abstract: An apparatus includes a first read port, a second read port, a write port, and at least one storage latch. A width of a bit cell that includes the first read port, the second read port, and the write port is greater than twice a contacted poly pitch (CPP) associated with the bit cell. For example, a bit cell may be a 3-port static random access memory (SRAM) bit cell that is compatible with self-aligned double patterning (SADP) processes and that can be manufactured using semiconductor manufacturing processes of less than 14 nanometers (nm).

Abstract translation: 一种装置包括第一读取端口，第二读取端口，写入端口和至少一个存储锁存器。 包括第一读取端口，第二读取端口和写入端口的位单元的宽度大于与位单元相关联的接触多边距（CPP）的两倍。 例如，位单元可以是与自对准双图案（SADP）工艺兼容的3端口静态随机存取存储器（SRAM）位单元，并且可以使用小于14纳米（nm）的半导体制造工艺来制造 ）。

公开(公告)号：US20150380080A1

公开(公告)日：2015-12-31

申请号：US14320024

申请日：2014-06-30

Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Choh Fei Yeap ,  Zhongze Wang

IPC: G11C11/419 ,  G11C5/06

CPC classification number: G11C11/419 ,  G11C5/02 ,  G11C7/00 ,  G11C7/20 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417

Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

Abstract translation: 静态随机存取存储器（SRAM）存储单元包括一对交叉耦合的反相器和耦合到该对交叉耦合的反相器的第一反相器的第一节点的选通晶体管。 门控晶体管的栅极耦合到第一字线。 门控晶体管被配置为响应于第一字线信号而选择性地将位线耦合到第一逆变器的第一节点。 第一反相器具有耦合到第二字线的第二节点。 第一个字线和第二个字线都是独立可控的。