公开(公告)号：US09601607B2

公开(公告)日：2017-03-21

申请号：US14225836

申请日：2014-03-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Daeik Daniel Kim ,  Bin Yang ,  Jonghae Kim ,  Daniel Wayne Perry

IPC: H03K17/687 ,  H01L29/739 ,  G05F3/16 ,  H01L27/07

CPC classification number: H01L29/7393 ,  G05F3/16 ,  H01L27/0705

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

公开(公告)号：US20150145592A1

公开(公告)日：2015-05-28

申请号：US14225836

申请日：2014-03-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Daeik Daniel Kim ,  Bin Yang ,  Jonghae Kim ,  Daniel Wayne Perry

IPC: H01L29/739 ,  G05F3/16

CPC classification number: H01L29/7393 ,  G05F3/16 ,  H01L27/0705

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.

Abstract translation: 一种方法包括根据场效应晶体管（FET）型操作，偏置第一栅极电压以使单相电流从晶体管的第一区域流过晶体管的第二区域。 该方法还包括偏置主体端子以使得双极电流能够根据双极结型晶体管（BJT）型操作从第一区域流动到第二区域。 单极电流与双极电流同时流动，在互补金属氧化物半导体（CMOS）技术中提供双模数字和模拟器件。

公开(公告)号：US09461055B2

公开(公告)日：2016-10-04

申请号：US14280213

申请日：2014-05-16

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Zhongze Wang ,  Daniel Wayne Perry

IPC: H01L27/112 ,  G11C11/40 ,  G11C7/00 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L27/112 ,  G11C7/00 ,  G11C11/40 ,  G11C16/0475 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/66833 ,  H01L29/7923

Abstract: An advanced metal-nitride-oxide-silicon (MNOS) multiple time programmable (MTP) memory is provided. In an example, an apparatus includes a two field effect transistor (2T field FET) metal-nitride-oxide-silicon (MNOS) MTP memory. The 2T field FET MNOS MTP memory can include an interlayer dielectric (ILD) oxide region that is formed on a well and separates respective gates of first and second transistors from the well. A control gate is located between the respective gates of the first and second transistors, and a silicon-nitride-oxide (SiN) region is located between a metal portion of the control gate and a portion of the ILD oxide region.

Abstract translation: 提供先进的金属氮化物 - 氧化物 - 硅（MNOS）多时间可编程（MTP）存储器。 在一个示例中，装置包括两个场效应晶体管（2T场FET）金属氮化物 - 氧化物 - 硅（MNOS）MTP存储器。 2T场FET MNOS MTP存储器可以包括形成在阱上的层间电介质（ILD）氧化物区域，并将第一和第二晶体管的相应栅极与阱分离。 控制栅极位于第一和第二晶体管的各个栅极之间，并且氮化硅 - 氧化物（SiN）区域位于控制栅极的金属部分和ILD氧化物区域的一部分之间。