公开(公告)号：US20220068906A1

公开(公告)日：2022-03-03

申请号：US17010001

申请日：2020-09-02

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song ,  Mohammed Yousuff Shariff

IPC: H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices. However, to avoid the need to route the power signals to semiconductor devices through the FS-BEOL metallization structure, thus increasing routing density and complexity the FS-BEOL metallization structure, the power signals are routed from the FS-BEOL metallization structure to the BS-BEOL metallization structure and to semiconductor devices for power.

公开(公告)号：US11244895B2

公开(公告)日：2022-02-08

申请号：US16889645

申请日：2020-06-01

Applicant: QUALCOMM Incorporated

Inventor： Ramesh Manchana ,  Sudheer Chowdary Gali ,  Biswa Ranjan Panda ,  Dhaval Sejpal ,  Stanley Seungchul Song

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L49/02

Abstract: A substrate tie cell on an IC is provided. The substrate tie cell includes a diffusion region. The diffusion region is a p-type diffusion region on or within a p-type substrate, an n-type diffusion region on or within an n-type well within a p-type substrate, an n-type diffusion region on or within an n-type substrate, or a p-type diffusion region on or within a p-type well within an n-type substrate. The substrate tie cell further includes a plurality of adjacent gate interconnects (n adjacent gate interconnects) extending over the diffusion region, where n≥4. The diffusion region is configured to be at one of a first voltage or a second voltage, and the gate interconnects are configured to be at an other of the first voltage or the second voltage. In one configuration, the first voltage is a power supply voltage and the second voltage is a ground voltage.

公开(公告)号：US10593700B2

公开(公告)日：2020-03-17

申请号：US15855996

申请日：2017-12-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L27/118 ,  H01L23/535 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

公开(公告)号：US20200058792A1

公开(公告)日：2020-02-20

申请号：US16104522

申请日：2018-08-17

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  Peijie Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

Abstract: Cell circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation and related methods are disclosed. In one aspect, a cell circuit includes a substrate of semiconductor material and a semiconductor channel structure(s) of a second semiconductor material disposed on the substrate. The semiconductor material applies a stress to the formed semiconductor channel structure(s) to induce a strain in the semiconductor channel structure(s) for increasing carrier mobility. A diffusion break comprising a dielectric material extends through a surrounding structure of an interlayer dielectric, and the semiconductor channel structure(s) and at least a portion of the substrate. The relaxation of strain in areas of the semiconductor channel structure(s) adjacent to the diffusion break is reduced or avoided, because the semiconductor channel structure(s) is constrained by the surrounding structure.

公开(公告)号：US10439039B2

公开(公告)日：2019-10-08

申请号：US15081702

申请日：2016-03-25

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Kern Rim ,  Choh Fei Yeap

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H01L29/161 ,  H01L29/423 ,  H01L29/786

Abstract: An integrated circuit includes a FinFET and a nanostructure FET. The integrated circuit includes a bulk substrate. The integrated circuit also includes a fin field effect transistor (FinFET) coupled to the bulk substrate. The FinFET includes a first source region, a first drain region, and a fin extending between the first source region and the first drain region. The integrated circuit also includes a nanostructure FET coupled to the bulk substrate. The nanostructure FET includes a second source region, a second drain region, and a stack of at least two nanostructures extending between the second source region and the second drain region.

公开(公告)号：US20190296126A1

公开(公告)日：2019-09-26

申请号：US15927343

申请日：2018-03-21

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul Song ,  Kern Rim ,  Da Yang ,  John Jianhong Zhu

IPC: H01L29/66 ,  H01L29/06 ,  H01L23/535 ,  H01L27/088 ,  H01L27/02 ,  H01L21/768 ,  H01L29/417

Abstract: Systems and methods for dummy gate tie-offs in a self-aligned gate contact (SAGC) cell are disclosed. In particular, exemplary aspects contemplate a two-part etching process to remove hardmasks formed from different materials from adjacent elements. A metal fill material may then be used to tie off the adjacent elements. The use of the two-part etching process allows SAGC techniques to be used for a first portion of a cell while still providing a technique to allow a tie-off in a second portion of the cell. The tie-off may be used with a dummy gate to provide isolation between cells.

公开(公告)号：US10163792B2

公开(公告)日：2018-12-25

申请号：US14444104

申请日：2014-07-28

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong Zhu ,  Jeffrey Junhao Xu ,  Choh Fei Yeap ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/321 ,  H01L23/522 ,  H01L23/532

Abstract: An apparatus includes a first interconnect and a first barrier structure. The first barrier structure is in contact with a dielectric material. The apparatus further includes a first protective structure in contact with the first barrier structure and an etch stop layer. An airgap is defined at least in part by the first protective structure and the etch stop layer.

公开(公告)号：US10157992B2

公开(公告)日：2018-12-18

申请号：US14980850

申请日：2015-12-28

Applicant: QUALCOMM Incorporated

Inventor： Mustafa Badaroglu ,  Vladimir Machkaoutsan ,  Stanley Seungchul Song ,  Jeffrey Junhao Xu ,  Matthew Michael Nowak ,  Choh Fei Yeap

IPC: H01L29/423 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/165 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/08

Abstract: A nanowire transistor is provided that includes a well implant having a local isolation region for insulating a replacement metal gate from a parasitic channel. In addition, the nanowire transistor includes oxidized caps in the extension regions that inhibit parasitic gate-to-source and gate-to-drain capacitances.

公开(公告)号：US09984029B2

公开(公告)日：2018-05-29

申请号：US14484137

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Kern Rim ,  Stanley Seungchul Song ,  Xiangdong Chen ,  Raymond George Stephany ,  John Jianhong Zhu ,  Ohsang Kwon ,  Esin Terzioglu ,  Choh Fei Yeap

IPC: H01L23/528 ,  G06F13/40 ,  G06F13/42 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

公开(公告)号：US09887209B2

公开(公告)日：2018-02-06

申请号：US14279250

申请日：2014-05-15

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L21/44 ,  H01L27/118 ,  H01L23/535 ,  H01L27/092 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.