公开(公告)号：US10366199B2

公开(公告)日：2019-07-30

申请号：US15484615

申请日：2017-04-11

Applicant: QUALCOMM Incorporated

Inventor： Jagadish Hosmani ,  Mohammed Yousuff Shariff ,  Venugopal Sanaka ,  Huibo Hou

IPC: H02J3/00 ,  G06F17/50 ,  H01L23/528 ,  H01L27/02

Abstract: Aspects of the disclosure are directed to a metal only cell-based power grid (PG) architecture. In accordance with one aspect, the power gird (PG) architecture includes a cell building block structure with a N×M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to one another; and a plurality of power grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.

公开(公告)号：US10109619B2

公开(公告)日：2018-10-23

申请号：US15174684

申请日：2016-06-06

Applicant: QUALCOMM Incorporated

Inventor： Harshat Pant ,  Mohammed Yousuff Shariff ,  Parissa Najdesamii ,  Ramaprasath Vilangudipitchai ,  Divjyot Bhan

IPC: H01L23/538 ,  H01L27/02 ,  H01L23/535 ,  H01L27/088 ,  G06F17/50 ,  H01L21/8238

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.

公开(公告)号：US20220068906A1

公开(公告)日：2022-03-03

申请号：US17010001

申请日：2020-09-02

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song ,  Mohammed Yousuff Shariff

IPC: H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices. However, to avoid the need to route the power signals to semiconductor devices through the FS-BEOL metallization structure, thus increasing routing density and complexity the FS-BEOL metallization structure, the power signals are routed from the FS-BEOL metallization structure to the BS-BEOL metallization structure and to semiconductor devices for power.

公开(公告)号：US11687106B1

公开(公告)日：2023-06-27

申请号：US17662460

申请日：2022-05-09

Applicant: QUALCOMM Incorporated

Inventor： Giby Samson ,  Harshat Pant ,  Keyurkumar Karsanbhai Kansagra ,  Mohammed Yousuff Shariff ,  Vinayak Nana Mehetre

IPC: G05F1/56 ,  G06F1/26 ,  H03K17/687

CPC classification number: G05F1/56 ,  G06F1/263 ,  H03K17/687

Abstract: A system on chip (SOC) includes a power distribution network (PDN) that has two different types of power multiplexers. The first power multiplexer type includes a lower resistance switching logic, and the second type includes a higher resistance switching logic as well as digital logic to provide an enable signal to the first type of power multiplexer. A given first-type power multiplexer may have multiple power multiplexers of the second type in a loop, the loop including communication paths for the enable signal and feeding the enable signal back to an enable input of the first-type power multiplexer.

公开(公告)号：US11270991B1

公开(公告)日：2022-03-08

申请号：US17010001

申请日：2020-09-02

Applicant: QUALCOMM Incorporated

Inventor： Bharani Chava ,  Stanley Seungchul Song ,  Mohammed Yousuff Shariff

IPC: H01L27/06 ,  H01L25/00 ,  H01L23/498 ,  H01L25/065 ,  H01L21/48

Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices. However, to avoid the need to route the power signals to semiconductor devices through the FS-BEOL metallization structure, thus increasing routing density and complexity the FS-BEOL metallization structure, the power signals are routed from the FS-BEOL metallization structure to the BS-BEOL metallization structure and to semiconductor devices for power.

公开(公告)号：US20180293344A1

公开(公告)日：2018-10-11

申请号：US15484615

申请日：2017-04-11

Applicant: QUALCOMM Incorporated

Inventor： Jagadish Hosmani ,  Mohammed Yousuff Shariff ,  Venugopal Sanaka ,  Huibo Hou

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068 ,  G06F17/5072 ,  G06F2217/08 ,  G06F2217/78 ,  H01L23/5286 ,  H01L27/0207 ,  H02J3/00

Abstract: Aspects of the disclosure are directed to a metal only cell-based power grid (PG) architecture. In accordance with one aspect, the power gird (PG) architecture includes a cell building block structure with a N×M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to one another; and a plurality of power grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.